lh28f128bfht-pbtl75a Sharp Microelectronics of the Americas, lh28f128bfht-pbtl75a Datasheet - Page 19

• Manufacturer Part Number: lh28f128bfht-pbtl75a
• Description: Flash Memory 16mbit 8mbitx16
• Manufacturer: Sharp Microelectronics of the Americas

SR.7 = PLANE WRITE STATE MACHINE STATUS
SR.6 = GLOBAL BLOCK ERASE SUSPEND STATUS
SR.5 = GLOBAL BLOCK ERASE AND
SR.4 = GLOBAL (PAGE BUFFER) PROGRAM AND
SR.3 = GLOBAL WP#/ACC STATUS (GWPACCS)
SR.2 = GLOBAL (PAGE BUFFER) PROGRAM
SR.1 = GLOBAL DEVICE PROTECT STATUS (GDPS)
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
GWSMS
PWSMS
1 = Ready
0 = Busy
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
1 = Error in Block Erase or Full Chip Erase
0 = Successful Block Erase or Full Chip Erase
1 = Error in (Page Buffer) Program or OTP Program
0 = Successful (Page Buffer) Program or OTP Program
1 = V
0 = WP#/ACC OK
1 = (Page Buffer) Program Suspended
0 = (Page Buffer) Program in Progress/Completed
1 = Erase or Program Attempted on a
0 = Unlocked
15
7
Operation Abort
Locked Block, Operation Abort
(PWSMS)
(GBESS)
FULL CHIP ERASE STATUS (GBEFCES)
SUSPEND STATUS (GPBPSS)
CCQ
OTP PROGRAM STATUS (GPBPOPS)
+0.4V < WP#/ACC < 9.0V Detect,
GBESS
GBESS
14
6
GBEFCES
GBEFCES
13
5
Table 9.1. Status Register Definition
GPBPOPS
GPBPOPS
12
4
LHF12F17
Status Register indicates the status of the WSM (Write State
Machine). However, SR.7 indicates the status of WSM in
each plane. Even if the SR.7 is "1", the WSM may be
occupied by the other plane.
In the plane to which the command is issued, Check SR.7 or
RY/BY# to determine block erase, full chip erase, (page
buffer) program or OTP program completion. SR.6 - SR.1 are
invalid while SR.7="0".
If both SR.5 and SR.4 are "1"s after a block erase, full chip
erase, (page buffer) program, set/clear block lock bit, set
block lock-down bit attempt, an improper command
sequence was entered.
SR.3 does not provide a continuous indication of WP#/ACC
level. The WSM interrogates and indicates the WP#/ACC
level only after Block Erase, Full Chip Erase, (Page Buffer)
Program or OTP Program command sequences. SR.3 is not
guaranteed to report accurate feedback when WP#/
ACC≠V
SR.1 does not provide a continuous indication of block lock
bit. The WSM interrogates the block lock bit only after Block
Erase, Full Chip Erase, (Page Buffer) Program or OTP
Program command sequences. It informs the system,
depending on the attempted operation, if the block lock bit is
set. Reading the block lock configuration codes after writing
the Read Identifier Codes/OTP command indicates block
lock bit status.
SR.0 is reserved for future use and should be masked out
when polling the status register.
GWPACCS
GWPACCS
11
3
ACCH
.
GPBPSS
GPBPSS
10
2
NOTES:
GDPS
GDPS
9
1
Rev. 0.04
R
R
8
0
16