m58bw32f STMicroelectronics, m58bw32f Datasheet - Page 21

• Manufacturer Part Number: m58bw32f
• Description: 16 Or 32 Mbit X32, Boot Block, Burst 3.3v Supply Flash Memories
• Manufacturer: STMicroelectronics

M58BW16F, M58BW32F
2.5
2.6
2.7
2.8
Output Disable (GD)
The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD, is at
V
outputs are high impedance independently of Output Enable. The Output Disable pin must
be connected to an external pull-up resistor as there is no internal pull-up resistor to drive
the pin.
Write Enable (W)
The Write Enable, W, input controls writing to the command interface, input address and
data latches. Both addresses and data can be latched on the rising edge of Write Enable
(also see Latch Enable, L).
Reset/Power-down (RP)
The Reset/Power-down, RP, is used to apply a hardware reset to the memory. A hardware
reset is achieved by holding Reset/Power-down Low, V
inhibited to protect data, the command interface and the Program/Erase controller are reset.
The Status Register information is cleared and power consumption is reduced to the
standby level (I
impedance.
After Reset/Power-down goes High, V
after a delay of t
If Reset/Power-down goes Low, V
internal state machine handles the operation as a Program/Erase Suspend, so the
maximum time defined
applied.
During power-up power should be applied simultaneously to V
at V
and Write Enable, W, should be held at V
In an application, it is recommended to associate the Reset/Power-down pin, RP, with the
reset signal of the microprocessor. Otherwise, if a Reset operation occurs while the memory
is performing an Erase or program operation, the memory may output the Status Register
information instead of being initialized to the default Asynchronous Random Read mode.
See
pins
Program/Erase Enable (PEN)
The Program/Erase Enable input, PEN, protects all blocks by preventing Program and Erase
operations from modifying the data.
Prior to issuing a Program or Erase command, the Program/Erase Enable must be set to
High (V
generated in the Status Register.
IH
, the outputs are driven by the Output Enable. When Output Disable, GD, is at V
IL
Table 24
Low, for more details.
. When the supplies are stable RP is taken to V
IH
). If it is Low (V
and
DD1
PHEL
Figure 22: Reset, Power-down and Power-up AC waveforms - Control
). The device acts as deselected, that is the data outputs are high
or Bus Write operations after t
inTable 12: Program, Erase times and endurance cycles
IL
), the Program or Erase operation is not accepted and an error is
IL
, during a Block Erase or a Program operation, the
IH
, the memory will be ready for Bus Read operations
IH
during power-up.
PHWL
IH
. Output Enable, G, Chip Enable, E,
IL
, for at least t
.
DD
and V
PLPH
Signal descriptions
DDQIN
. Writing is
with RP held
must be
IL
, the
21/87