m58bw32f STMicroelectronics, m58bw32f Datasheet - Page 25

• Manufacturer Part Number: m58bw32f
• Description: 16 Or 32 Mbit X32, Boot Block, Burst 3.3v Supply Flash Memories
• Manufacturer: STMicroelectronics

M58BW16F, M58BW32F
3.1.3
3.1.4
3.1.5
3.1.6
Asynchronous Page Read
Asynchronous Page Read operations are used to read from several addresses within the
same memory page. Each memory page is 4 double-words and is addressed by the
address inputs A0 and A1.
Data is read internally and stored in the page buffer. Valid bus operations are the same as
Asynchronous Bus Read operations but with different timings. The first read operation within
the page has identical timings, subsequent reads within the same page have much shorter
access times. If the page changes then the normal, longer timings apply again. Page Read
does not support Latched Controlled Read.
See
Page Read AC
Asynchronous Bus Write
Asynchronous Bus Write operations write to the command interface in order to send
commands to the memory or to latch addresses and input data to program. Bus Write
operations are asynchronous, the clock, K, is don’t care during Bus Write operations.
A valid Asynchronous Bus Write operation begins by setting the desired address on the
Address inputs, and setting Chip Enable, Write Enable and Latch Enable Low, V
Output Enable High, V
command interface on the rising edge of Chip Enable or Write Enable, whichever occurs
first. Commands and input data are latched on the rising edge of Chip Enable, E, or Write
Enable, W, whichever occurs first. Output Enable must remain High, and Output Disable
Low, during the whole Asynchronous Bus Write operation.
See
Latch controlled Write AC
Asynchronous Latch Controlled Bus Write
Asynchronous Latch Controlled Bus Write operations write to the command interface in
order to send commands to the memory or to latch addresses and input data to program.
Bus Write operations are asynchronous, the clock, K, is Don’t care during Bus Write
operations.
A valid Asynchronous Latch Controlled Bus Write operation begins by setting the desired
address on the Address inputs and pulsing Latch Enable Low, V
latched by the command interface on the rising edge of Latch Enable, Write Enable or Chip
Enable, whichever occurs first. Commands and input data are latched on the rising edge of
Chip Enable, E, or Write Enable, W, whichever occurs first. Output Enable must remain
High, and Output Disable Low, during the whole Asynchronous Bus Write operation.
See
Asynchronous Write and Latch controlled Write AC
requirements.
Output Disable
The data outputs are high impedance when the Output Enable, G, is at V
Disable, GD, is at V
Figure 11: Asynchronous Page Read AC
Figure 12: Asynchronous Write AC
Figure 13: Asynchronous Latch controlled Write AC
characteristics, for details on when the outputs become valid.
IL
.
IH
, or Output Disable Low, V
characteristics, for details of the timing requirements.
waveforms, and
waveforms, and
IL
characteristics, for details of the timing
. The Address inputs are latched by the
Table 21: Asynchronous Write and
waveforms, and
Table 20: Asynchronous
IL
. The Address inputs are
IH
Table 21:
Bus operations
or Output
IL
, and
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