m58bw32f STMicroelectronics, m58bw32f Datasheet - Page 27

• Manufacturer Part Number: m58bw32f
• Description: 16 Or 32 Mbit X32, Boot Block, Burst 3.3v Supply Flash Memories
• Manufacturer: STMicroelectronics

M58BW16F, M58BW32F
3.2
3.2.1
Synchronous Bus operations
For Synchronous Bus Operations refer to
access will start at whichever of the three following events occurs last: valid address
transition, Chip Enable, E, going Low, V
Synchronous Burst Read
Synchronous Burst Read operations are used to read from the memory at specific times
synchronized to an external reference clock. The valid edge of the Clock signal is the rising
edge. Once the Flash memory is configured in Burst mode, it is mandatory to have an active
clock signal since the switching of the output buffer databus is synchronized to the rising
edge of the clock. In the absence of clock, no data is output.
The burst type, length and latency can be configured. The different configurations for
Synchronous Burst Read operations are described in the Burst Configuration Register
section. Refer to
A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip
Enable and Latch Enable are Low, V
the internal Burst Address counter on the valid Burst Clock K edge or on the rising edge of
Latch Enable, whichever occurs first.
After an initial memory latency time, the memory outputs data each clock cycle. The Burst
Address Advance B input controls the memory burst output. The second burst output is on
the next clock valid edge after the Burst Address Advance B has been pulled Low.
Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst
Controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low
on the rising clock edge, no new data is available and the memory does not increment the
internal address counter at the active clock edge even if Burst Address Advance, B, is Low.
Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid
immediately at the rising clock edge.
Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, V
If Output Enable is at V
If Output Enable, G, is at V
Advance, B, is at V
K rising edge.
The Synchronous Burst Read timing diagrams and AC characteristics are described in the
AC and DC parameters section. See Figures 14, 17,
Figure 4
IL
the internal Burst Address counter is incremented at each Burst Clock
IL
and Output Disable is at V
for examples of Synchronous Burst operations.
IH
or Output Disable, GD, is at V
IL
. The burst start address is latched and loaded into
IL
Table 7
or Latch Enable, L, going Low, V
together with the following text. The read
IH
18
, the last data is still valid.
and 19, and
IL
, but the Burst Address
Table
IL
22.
Bus operations
.
27/87
IH
.