m58bw016bt STMicroelectronics, m58bw016bt Datasheet - Page 17

no-image

m58bw016bt

Manufacturer Part Number
m58bw016bt
Description
16 Mbit 512kb X32, Boot Block, Burst 3v Supply Flash Memories
Manufacturer
STMicroelectronics
Datasheet
Table 5. Asynchronous Read Electronic Signature Operation
Note: 1. x= B or D version of the device.
Synchronous Bus Operations
For synchronous bus operations refer to Table 6
together with the following text.
Synchronous Burst Read. Synchronous Burst
Read operations are used to read from the memo-
ry at specific times synchronized to an external ref-
erence clock. The burst type, length and latency
can be configured. The different configurations for
Synchronous Burst Read operations are de-
scribed in the Burst Configuration Register sec-
tion. Refer to Figures 5 and 6 for examples of
synchronous burst operations.
In continuous burst read, one burst read operation
can access the entire memory sequentially by
keeping the Burst Address Advance B at V
the appropriate number of clock cycles. At the end
of the memory address space the burst read re-
starts from the beginning at address 000000h.
A valid Synchronous Burst Read operation begins
when the Burst Clock is active and Chip Enable
and Latch Enable are Low, V
dress is latched and loaded into the internal Burst
Address Counter on the valid Burst Clock K edge
(rising or falling depending on the value of M6) or
on the rising edge of Latch Enable, whichever oc-
curs first.
After an initial memory latency time, the memory
outputs data each clock cycle (or two clock cycles
depending on the value of M9). The Burst Address
Advance B input controls the memory burst output.
The second burst output is on the next clock valid
edge after the Burst Address Advance B has been
pulled Low.
Valid Data Ready, R, monitors if the memory burst
boundary is exceeded and the Burst Controller of
the microprocessor needs to insert wait states.
Burst Configuration
Manufacturer
2. BCR= Burst Configuration Register.
Register
Device
Code
M58BW016xB
M58BW016xT
Device
All
IL
. The burst start ad-
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
(1)
(1)
V
V
V
V
E
IL
IL
IL
IL
IL
for
V
V
V
V
G
IL
IL
IL
IL
When Valid Data Ready is Low on the active clock
edge, no new data is available and the memory
does not increment the internal address counter at
the active clock edge even if Burst Address Ad-
vance, B, is Low.
Valid Data Ready may be configured (by bit M8 of
Burst Configuration Register) to be valid immedi-
ately at the valid clock edge or one data cycle be-
fore the valid clock edge.
Synchronous Burst Read will be suspended if
Burst Address Advance, B, goes High, V
If Output Enable is at V
V
If Output Enable, G, is at V
GD, is at V
at V
mented at each Burst Clock K valid edge.
The Synchronous Burst Read timing diagrams
and AC Characteristics are described in the AC
and DC Parameters section. See Figures 14, 15,
16 and 17, and Table 20.
Synchronous Burst Read Suspend. During
Synchronous Burst Read operation it is possible to
suspend the operation, freeing the data bus for
other higher priority devices.
A valid Synchronous Burst Read operation is sus-
pended when both Output Enable and Burst Ad-
dress Advance are High, V
Advance going High, V
and the Output Enable going High, V
data outputs. The Synchronous Burst Read oper-
ation can be resumed by setting Output Enable
Low.
IH
, the last data is still valid.
IL
the internal Burst Address Counter is incre-
GD
V
V
V
V
IH
IH
IH
IH
IL
, but the Burst Address Advance, B, is
V
V
V
V
W
IH
IH
IH
IH
IH
IL
, stops the burst counter
and Output Disable is at
IH
A18-A0
00000h
00001h
00001h
00005h
IH
. The Burst Address
or Output Disable,
IH
, inhibits the
DQ31-DQ0
00000020h
00008836h
00008835h
BCR
IH
.
17/63
(2)
a

Related parts for m58bw016bt