m58bw016bt STMicroelectronics, m58bw016bt Datasheet - Page 25

• Manufacturer Part Number: m58bw016bt
• Description: 16 Mbit 512kb X32, Boot Block, Burst 3v Supply Flash Memories
• Manufacturer: STMicroelectronics

Asynchronous Read mode and the valid Clock
edge configuration.
Two Bus Write cycles are required to issue the Set
Burst Configuration Register command. The first
cycle writes the setup command and the address
corresponding to the Set Burst Configuration Reg-
ister content. The second cycle writes the Burst
Configuration Register data and the confirm com-
mand. Once the command is issued the memory
returns to Read mode as if a Read Memory Array
command had been issued.
The value for the Burst Configuration Register is
always presented on A0-A15. M0 is on A0, M1 on
A1, etc.; the other address bits are ignored.
Tuning Protection Unlock Command
The Tuning Protection Unlock command unlocks
the tuning protected blocks by writing the 64bit
Tuning Protection Code (M58BW016B only). After
a reset or power-up the blocks are locked and so
a Tuning Protection Unlock command must be is-
sued to allow program or erase operations on tun-
ing protected block or to program a new Tuning
Protection Code. Read operations output the Sta-
tus Register content after the unlock operation has
started.
The Tuning Protection Code is composed of 64
bits, but the data bus is 32 bits wide so four (2 x 2)
write cycles are required to unlock the device.
Bit 7 of the Status Register should now be
checked to verify that the device has successfully
stored the first part of the code in the internal reg-
ister. If b7 = ‘1’, the device is ready to accept the
second part of the code. This does not mean that
the first 32 bits match the tuning protection code,
simply that it was correctly stored for the compar-
ing. If b7 = ‘0’, the user must wait for this bit setting
(refer to write cycle AC timings).
Bit 7 of the Status Register should again be
checked to verify that the device has successfully
stored the second part of the code. When the de-
vice is ready (b7 = ‘1’), the tuning protection status
can be monitored on Status Register bit0. If b0 =
‘0’ the device is locked; b0 = ‘1’ the device is un-
locked. If the device is still locked a Read Memory
Array command must be issued before re-issuing
the Tuning Protection Unlock command.
The first write cycle issues the Tuning
Protection Unlock Setup command (0x78).
The second write cycle inputs the first 32 bits of
the tuning protection code on the data bus, at
address 0x00000.
The third write cycle re-issues the Tuning
Protection Unlock Setup command (0x78).
The fourth write cycle inputs the second 32 bits
of the code at address 0x00001.
M58BW016BT, M58BW016BB, M58BW016DT, M58BW016DB
Device locked means that the 64 bit password is
Once the device is successfully unlocked, a Read
Memory Array command must be issued to return
the memory to read mode before issuing any other
commands. The user can then program or erase
all blocks, depending on WP status and V
At this point, it is also possible to configure a new
protection code. To write a new protection code
into the device tuning register, the user must per-
form the Tuning Protection Program sequence.
The device can be re-locked with a reset or power-
down.
See Appendix B, Figure 25, 26 and 27 for suggest-
ed flowcharts for using the Tuning Protection Un-
lock command.
Tuning Protection Program Command.
The Tuning Protection Program command is used
to program a new Tuning Protection Code which
can be configured by the designer of the applica-
tion (M58BW016B only). The device should be un-
locked by the Tuning Protection Unlock command
before issuing the Tuning Protection Program
command.
Read operations output the Status Register con-
tent after the program operation has started.
The Tuning Protection Code is composed of 64
bits, but the data bus is 32 bits wide so four (2 x 2)
write cycles are required to program the code.
Bit 7 of the Status Register should now be
checked to verify that the device has successfully
stored the first part of the code in the internal reg-
ister. If b7 = ‘1’, the device is ready to accept the
second part of the code. If b7 = ‘0’, the user must
wait for this bit setting (refer to write cycle AC tim-
ings).
Bit 7 of the Status Register should again be
checked to verify that the device has successfully
stored the second part of the code. When the de-
vice is ready (b7 = ‘1’). After completion Status
wrong. If the unlock operation is attempted using a
wrong code on an already unlocked device, the
device becomes locked. Status register bit 4 is set
to '1' if there has been a verify failure.
Unlocking aborts if V
range or RP goes to V
The first write cycle issues the Tuning
Protection Program Setup command (0x48).
The second write cycle inputs the first 32 bits of
the new tuning protection code on the data bus,
at address 0x00000.
The third write cycle re-issues the Tuning
Protection Program Setup command (0x48).
The fourth write cycle inputs the second 32 bits
of the new code at address 0x00001.
PP
IL
.
drops out of the allowed
PP
level.
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