m58bw016 Numonyx, m58bw016 Datasheet
m58bw016
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m58bw016 Summary of contents
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... Low power consumption – 5 µA typical deep power-down – 60 µA typical standby for M58BW016DT/B 150 µA typical standby for M58BW016FT/B – Automatic standby after asynchronous read ■ Electronic signature – Manufacturer code: 20h – ...
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... Ground (V 2.18 Don’t use (DU 2.19 Not connected (NC Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 Asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 2/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DD DDQ ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DDQIN ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PP and SSQ Asynchronous bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Asynchronous latch controlled bus read . . . . . . . . . . . . . . . . . . . . . . . . 18 Asynchronous page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Asynchronous bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Asynchronous latch controlled bus write . . . . . . . . . . . . . . . . . . . . . . . . 19 ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 3.1.7 3.1.8 3.1.9 3.1.10 3.2 Synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 3.2.2 3.3 Burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 4 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 Read Memory Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 Read Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.7 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.8 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.9 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4 ...
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... Contents 5.6 Program suspend status (bit 5.7 Block protection status (bit Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Appendix A Common Flash interface (CFI Appendix B Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 2. M58BW016DT and M58BW016FT top boot block addresses . . . . . . . . . . . . . . . . . . . . . . 12 Table 3. M58BW016DB and M58BW016FB bottom boot block addresses . . . . . . . . . . . . . . . . . . . 13 Table 4. Asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 5. Asynchronous read electronic signature operation Table 6. Synchronous burst read bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 7 ...
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... Power-up sequence followed by synchronous burst read . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 27. Command interface and program/erase controller flowchart (a Figure 28. Command interface and program/erase controller flowchart (b Figure 29. Command interface and program/erase controller flowchart (c Figure 30. Command interface and program/erase controller flowchart (d 6/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB ...
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... The devices have a boot block architecture with an array of 8 parameter blocks of 64 Kbits each and 31 main blocks of 512 Kbits each. In the M58BW016DT and M58BW016FT the parameter blocks are located at the top of the address space whereas in the M58BW016DB and M58BW016FB, they are located at the bottom ...
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... Description Figure 1. Logic diagram 8/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB DDQ V DDQIN V PP A0-A18 M58BW016DT M58BW016DB RP M58BW016FT M58BW016FB SSQ DQ0-DQ31 R AI11201b ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 1. Signal names Signal A0-A18 DQ0-DQ7 DQ8-DQ15 DQ16-DQ31 DDQ V DDQIN SSQ NC DU Description Address inputs Data input/output, command input Data input/output, Burst Configuration Register Data input/output Burst Address Advance ...
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... DQ18 DQ19 V DDQ V SSQ DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 V DDQ V SSQ DQ28 DQ29 DQ30 DQ31 10/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 1 M58BW016DT 12 M58BW016DB M58BW016FT M58BW016FB 24 DQ15 64 DQ14 DQ13 DQ12 V SSQ V DDQ DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 53 DQ5 ...
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... DQ15 J V DDQIN 1.1 Block protection The M58BW016 feature two different levels of block protection. ● Write protect pin When WP is Low, V upper (top) or lower (bottom)) and all the main blocks are protected. When WP is High (V ) all the lockable parameter blocks and all the main blocks are unprotected IH ● ...
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... Description Table 2. M58BW016DT and M58BW016FT top boot block addresses # 12/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Size (Kbit 512 512 512 ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 3. M58BW016DB and M58BW016FB bottom boot block addresses # Size (Kbit) 512 512 512 512 512 512 512 512 ...
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... Output Enable (G) The Output Enable, G, gates the outputs through the data output buffers during a read operation, when Output Disable are high impedance independently of Output Disable. 14/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB diagram, and Table 1: Signal names , Output Enable The status register content is output on DQ0-DQ7 and DQ8- ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 2.5 Output Disable (GD) The Output Disable, GD, deactivates the data output buffers. When Output Disable, GD the outputs are driven by the Output Enable. When Output Disable, GD outputs are high impedance independently of Output Enable. The Output Disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin ...
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... IH 2.13 Supply voltage (V The supply voltage, V the V pin, including the program/erase controller. DD 16/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB . IL IL the first two (in the bottom configuration) or last two (in the top the core power supply. All internal circuits draw their current from ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 2.14 Output supply voltage (V The output supply voltage, V program and erase) used for DQ0-DQ31 when used as outputs. 2.15 Input supply voltage (V The input supply voltage GD A0-A18 and DQ0-DQ31, when used as inputs. 2.16 Program/erase supply voltage (V The program/erase supply voltage, V ...
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... Note that, since the Latch Enable input is transparent when set Low, V read operations can be performed when the memory is configured for asynchronous latch enable bus operations by holding Latch Enable Low, V 18/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Bus operations, for a summary. The bus operation is selected through Table 4 together with the following text. ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 3.1.3 Asynchronous page read Asynchronous page read operations are used to read from several addresses within the same memory page. Each memory page is 4 double-words and is addressed by the address inputs A0 and A1. Data is read internally and stored in the page buffer. Valid bus operations are the same as asynchronous bus read operations but with different timings ...
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... Asynchronous page read Asynchronous bus write Asynchronous latch controlled bus write Output Enable, G Output Disable, GD Standby Reset/power-down don’t care. 20/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB , and the Program/Erase controller is idle, the memory enters IH (1) Step ...
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... Synchronous burst read operations are used to read from the memory at specific times synchronized to an external reference clock. In the M58BW016FT and M58BW016FB only, once the memory is configured in burst mode mandatory to have an active clock signal since the switching of the output buffer data bus is synchronized to the active edge of the clock. In the absence of clock, no data is output ...
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... X = don't care M15 = 0, bit M15 is in the burst configuration register transition, see M6 in the burst configuration register for details on the active edge of K. 22/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB and Output Disable Output Disable, GD the internal Burst Address counter is incremented at each Burst Clock ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 3.3 Burst configuration register The burst configuration register is used to configure the type of bus access that the memory will perform. The burst configuration register is set through the command interface and will retain its information until it is re-configured, the device is reset, or the device goes into reset/power- down mode ...
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... M10, M5 and M4 are reserved for future use. 24/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB gives the valid combinations of the burst length bits that Table 8: Burst type definition, gives the sequence of addresses output ...
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... This feature is available for the M58BW016F version up to the full operative frequency of 56 MHz, and for the M58BW016D version only if the operative frequency is below 45 MHz. 3. The M58BW016F version has a maximum operative frequency of 66 MHz, fully factory tested. ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB x 8 sequential 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 – 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 – 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 – 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 – 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 – – – 0-1-2-3-4-5-6-7 – 1-2-3-4-5-6-7-8 – 2-3-4-5-6-7-8-9 – 3-4-5-6-7-8-9-10 – 4-5-6-7-8-9-10-11 – 5-6-7-8-9-10-11-12 – 6-7-8-9-10-11-12-13 – 7-8-9-10-11-12-13-14 – 8-9-10-11-12-13-14- Continuous interleaved 0-1-2-3-4-5-6-7-8-9-10 ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 4. Example burst configuration X-1-1 ADD VALID L DQ 4-1-1-1 DQ 5-1-1-1 DQ 6-1-1-1 DQ 7-1-1-1 DQ 8-1-1-1 Figure 5. Example burst configuration X-2-2 ADD VALID L DQ 5-2-2-2 DQ 6-2-2-2 DQ 7-2-2-2 DQ 8-2-2 VALID VALID VALID VALID NV NV=NOT VALID Bus operations VALID VALID VALID VALID ...
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... Flash interface memory area. See interface (CFI), Table information contained in the common Flash interface (CFI) memory area. 28/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Commands. Refer to Table 9 operation. 26, Table 27, ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 4.4 Read Status Register command The Read Status Register command is used to read the status register. One bus write cycle is required to issue the Read Status Register command. Once the command is issued subsequent bus read operations read the status register until another command is issued. ...
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... V PP program operation is aborted, the memory block must be erased and reprogrammed. See Appendix B: Flowcharts on page a suggested flowchart on using the Program command. 30/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB (for a normal erase operation the V range when the command is issued then a fast erase PP PPH ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 4.8 Program/Erase Suspend command The Program/Erase Suspend command is used to pause a program or erase operation. The command will only be accepted during a program or erase operation. It can be issued at any time during a program or erase operation. The command is ignored if the device is already in suspend mode. ...
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... Set Burst Configuration Register Don’t care Read Address Read Data Device Code, SRD = Status Register Data Program Address Program Data Query Address Query Data Any address in the Block, BCR = Burst Configuration Register value. 32/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB (1) 1st cycle Op. Addr. ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 10. Program, erase times and program, erase endurance cycles Parameters Parameter Block (64 Kbits) Program Main Block (512 Kbits) Program Parameter Block Erase Main Block Erase Program Suspend Latency time Erase Suspend Latency time Program/Erase cycles (per block – ...
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... Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the erase suspend status bit returns to ‘0’. 34/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB , and Output Disable Table 11: Status register ) and IH ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 5.3 Erase status (bit 5) The erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. The erase status bit should be read once the program/erase controller status bit is High (program/erase controller inactive). ...
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... Program status status PP 2 Program suspend status Erase/program in a protected 1 block Other bits reserved 36/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Name Logic level ’1’ ’0’ ’1’ ’0’ ’1’ ’0’ ’1’ ’0’ ’1’ ’0’ ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB 6 Maximum ratings Stressing the device above the ratings listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Clock rise and fall times Input rise and fall times Input pulses voltages Input and output timing ref. voltages Figure 6. AC measurement input/output waveform DDQ 38/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB conditions. Designers should check that the Parameter ) ) DDQ Grade Grade ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 7. AC measurement load circuit Table 14. Device capacitance Symbol C Input capacitance IN C Output capacitance OUT ° MHz Sampled only, not 100% tested. 1.3 V 1N914 3.3 k DEVICE UNDER TEST C L includes JIG capacitance (1)(2) Parameter Test condition ...
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... PP V PPLK program lockout defined only during the power-up phase of the M58BW016FT/B, from the moment current is applied with RP Low DDP-UP to the moment when the supply voltage has become stable and RP is brought to High. 40/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Test condition ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 8. Asynchronous bus read AC waveforms A0-A18 DQ0-DQ31 . Table 16. Asynchronous bus read AC characteristics Symbol t Address Valid to Address Valid AVAV t Address Valid to Output Valid AVQV t Address Transition to Output Transition AXQX t Chip Enable High to Latch Enable Transition EHLX ...
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... Latch Enable High to Latch Enable Low LHLL t Latch Enable Low to Latch Enable High LLLH t Latch Enable Low to Output Valid LLQV t Latch Enable Low to Output Transition LLQX 42/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB VALID tLHAX tLLLH tELLL tGLQX tGLQV tLLQX tLLQV Parameter Test condition ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 10. Asynchronous page read AC waveforms A0-A1 DQ0-DQ31 Table 18. Asynchronous page read AC characteristics Symbol t Address Valid to Output Valid AVQV1 t Address Transition to Output Transition AXQX 1. For other timings see A0 and/or A1 tAVQV1 tAXQX OUTPUT Parameter Table 16: Asynchronous bus read AC ...
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... DC and AC parameters Figure 11. Asynchronous write AC waveforms 44/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 12. Asynchronous latch controlled write AC waveforms DC and AC parameters 45/70 ...
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... Write Enable High to Output Valid WHQV t Write Enable High to Write Enable Low WHWL t Write Enable Low to Write Enable High WLWH t Output Valid to Reset/Power-down Low QVPL 46/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Parameter Test condition Low M58BW016 Unit ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 13. Synchronous burst read (data valid from ‘n’ clock rising edge) 1. The M58BW016F first data output is synchronized with the clock’s active edge, while the M58BW016D first data output is not synchronized with the clock’s active edge. ...
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... Data output should be read on the valid clock edge. Figure 14. Synchronous burst read (data valid from ‘n’ clock rising edge) K tKHQV DQ0-DQ31 SETUP Note: n depends on Burst X-Latency 1. For set up signals and timings see synchronous burst read. 48/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Parameter ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 15. Synchronous burst read - continuous - valid data ready output K (1) Output Valid Data Ready = Valid Low during valid clock edge Valid output open drain output with an internal pull up resistor typically 300 k for a single memory on the R bus, should be used to give the data valid set up time required to recognize that valid data is available on the next valid clock edge ...
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... Figure 17. Reset, power-down and power-up AC waveforms - control pins low tVDHPH VDD, VDDQ Figure 18. Reset, power-down and power-up AC waveforms - control pins toggling tVDHPH VDD, VDDQ 50/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB tPHLL tPHWL tPHEL tPHGL Hi-Z tPHRH Power-up tPHLL tPHWL tPHEL tPHGL Hi-Z tPHRH Power-up tPLRZ Hi-Z ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 19. Power supply slope specification Voltage VDHH VDH 1. Please refer to the application note AN2601. Table 21. Power supply AC and DC characteristics Symbol V Minimum value of power supply DH V Maximum value of power supply DHH t Time required from power supply to reach the V VDH Table 22 ...
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... JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. Figure 20. PQFP80 - 80 lead plastic quad flat pack, package outline Nd QFP-B 1. Drawing is not to scale. 52/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB ® packages are lead-free. The category of second level interconnect ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 23. PQFP80 - 80 lead plastic quad flat pack, package mechanical data Symbol millimeters Typ Min Max 3.40 0.25 2.80 2.55 3.05 0.30 0.45 0.13 0.23 23.20 22.95 23.45 20.00 19.90 20.10 18.40 – – 0.80 – – 17.20 16.95 17.45 14.00 13.90 14.10 12.00 – – 0.80 0.65 0.95 1.60 – – 0° 7° Package mechanical ...
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... Drawing is not to scale. Table 24. LBGA80 10 × × 10 active ball array pitch, package mechanical data Symbol ddd 54/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB BALL "A1" millimeters Typ Min Max 1.60 0.40 1.05 0.60 10.00 – – 7.00 – ...
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... T = PQFP80 ZA = LBGA 10 × Temperature range 3 = automotive grade certified Version F = silicon version F (only available in the M58BW016D devices) Option T = Tape and reel packing F = ECOPACK package, tape and reel packing 1. Qualified & characterized according to AEC Q100 & Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent. ...
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... The byte address and the word address mode are not available. 2. Query data are always presented on DQ7-DQ0. DQ31-DQ8 are set to '0'. 56/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 26, Table Sub-section name Data 51h "Q" 51h; ‘Q’ ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Table 28. CFI - device voltage and timing specification Address A0-A18 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h-24h 25h 26h 1. Bits are coded in binary code decimal, bit7 to bit4 are scaled in Volts and bit3 to bit0 in mV. 2. Bit7 to bit4 are coded in hexadecimal and scaled in Volts while bit3 to bit0 are in binary code decimal and scaled in 100 mV ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Data (Hex) 50h "P" 52h "R" Query ASCII string - extended table 49h "Y" 31h Major version number 31h Minor version number Optional feature: (1=yes, 0=no) bit0, Chip Erase supported (0=no) ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Appendix B Flowcharts Figure 22. Program flowchart and pseudocode Start Write 40h Write Address & Data Read Status Register YES YES YES YES End error is found, the status register must be cleared before further program/erase operations. ...
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... Register YES YES Write FFh Read data from another block Write D0h Program Continues 60/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB NO NO Program Complete Write FFh Read Data Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 24. Block erase flowchart and pseudocode Start Write 20h Write Block Address & D0h Read Status Register YES YES b4 and YES YES End error is found, the status register must be cleared before further program/erase operations. ...
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... YES YES Write FFh Read data from another block or Program Write D0h Erase Continues 62/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB NO NO Erase Complete Write FFh Read Data Program/Erase Suspend Command: – write B0h – write 70h do: – read status register while ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 26. Power-up sequence followed by synchronous burst read Power-up or Reset Asynchronous Read Write 60h command Write 03h with A15-A0 BCR inputs Synchronous Read BCR bit 15 = '1' Set Burst Configuration Register Command: – write 60h – write 03h and BCR on A15-A0 ...
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... Figure 27. Command interface and program/erase controller flowchart (a) WAIT FOR COMMAND WRITE NO 90h YES READ ELEC. 98h SIGNATURE READ CFI ERASE COMMAND ERROR READ STATUS B 64/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB NO YES NO 70h YES READ NO 20h STATUS YES ERASE SET-UP NO D0h YES A READ ARRAY ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 28. Command interface and program/erase controller flowchart ( 60h YES NO FFh SET BCR SET_UP YES NO 03h YES Flowcharts D AI03836b 65/70 ...
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... Flowcharts Figure 29. Command interface and program/erase controller flowchart ( READ STATUS READ ARRAY 66/70 M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB YES ERASE SUSPENDED YES YES 70h NO YES PROGRAM 40h SET_UP NO NO YES READ D0h STATUS A ERASE YES READY NO NO READ B0h STATUS YES ERASE ...
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... M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB Figure 30. Command interface and program/erase controller flowchart ( READ STATUS READ ARRAY YES YES PROGRAM SUSPENDED YES YES 70h NO NO YES READ D0h STATUS Flowcharts C PROGRAM READY NO NO READ B0h STATUS YES PROGRAM SUSPEND READY NO READ STATUS ...
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... Temperature rage 6 removed from scheme. Load capacitance updated in 9 conditions. Updated Table 25: Ordering information scheme on page 55 10 Disclaimer information. Converted document to new template. M58BW016FT and M58BW016FB part numbers added. Small text 11 changes. Changes (Table 12). (Table 16, Table 17, ...
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... Table 31. Document revision history (continued) Date Version 09-Nov-2006 24-Nov-2006 05-Oct-2007 16-Jan-2008 12-Mar-2008 26-Mar-2008 LBGA80 package added (see M58BW016FT and M58BW016FB behavior in Burst mode specified under Section 3.2.1: Synchronous burst and I current values specified for M58BW016FT and DDB DD1 DD4 M58BW016FB in Table 15: DC ...
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