m5m51016btp Renesas Electronics Corporation., m5m51016btp Datasheet - Page 250
m5m51016btp
Manufacturer Part Number
m5m51016btp
Description
Renesas 16-bit Single-chip Microcomputer M16c Family / M16c/20 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M5M51016BTP.pdf
(367 pages)
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M30245 Group
Rev.2.00 Oct 16, 2006
REJ09B0340-0200
Figure 2.10.1. Memory map of DMAC-related registers
(6) Reading to a register
(7) Switching function
(8) Registers related to DMAC
The reload register can be read to, as in normal conditions.
(a) Switching between one-shot transfer and repeated transfer
• A fixed address from an arbitrary 1M byte space, one-shot transfer
• An arbitrary 1M byte space from a fixed address, repeated transfer
Figure 2.10.1 shows the memory map of DMAC-related registers, and Figures 2.10.2 and 2.10.4 show
DMAC-related registers.
002C
003C
004C
004E
0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0050
0052
'One-shot transfer' refers to a mode in which DMA is disabled after the transfer counter underflows.
'Repeated transfer' refers to a mode in which a reload is carried out after the transfer counter under-
flows. The reload is carried out for the transfer counter and on the address pointer subjected to
forward direction.
The following examples are described in section 2.10.2 and 2.10.3.
16
16
16
16
16
16
16
16
16
16
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
DMA0 destination pointer (DAR0)
DMA0 transfer counter (TCR0)
DMA0 control register (DM0CON)
DMA1 control register (DM1CON)
DMA0 interrupt control register (DM0IC)
DMA1 interrupt control register (DM1IC)
DMA1 source pointer (SAR1)
DMA0 source pointer (SAR0)
DMA1 destination pointer (DAR1)
DMA1 transfer counter (TCR1)
DMA2 interrupt control register (DM2IC)
DMA3 interrupt control register (DM3IC)
page 241 of 354
018C
019C
03BA
03B0
03B1
03B2
03B8
03B9
0180
0181
0182
0183
0184
0185
0186
0187
0198
0189
0190
0191
0192
0193
0194
0195
0196
0197
0198
0199
16
16
16
16
16
16
16
16
16
16
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
DMA2 source pointer (SAR2)
DMA3 control register (DM3CON)
DMA2 cause select register (DM2SL)
DMA3 cause select register (DM3SL)
DMA2 destination pointer (DAR2)
DMA3 transfer counter (TCR3)
DMA0 cause select register (DM0SL)
DMA1 cause select register (DM1SL)
DMA3 destination pointer (DAR3)
DMA2 transfer counter (TCR2)
DMA2 control register (DM2CON)
DMA3 source pointer (SAR3)
2. DMAC
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