mt28f640j3rp-115-met Micron Semiconductor Products, mt28f640j3rp-115-met Datasheet
mt28f640j3rp-115-met
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mt28f640j3rp-115-met Summary of contents
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... TSOP Type I • 64-ball (standard) FBGA (1.00mm pitch) • 64-ball (lead-free) FBGA (1.00mm pitch) Manufacturer’s Identification Code (ManID) • Micron (0x2Ch) • Intel (0x89h) MT28F640J3RG-115ET 1 128Mb, 64Mb, 32Mb Q-FLASH MEMORY Mark Part Number Example: ©2000 Micron Technology, Inc. -11 -115 - ...
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... Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Reducing Overshoots and Undershoots When Using Buffers or Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Vcc, Vpen, and RP# Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN 128Mb, 64Mb, 32Mb Q-FLASH MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. 2 ©2000 Micron Technology. Inc. ...
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... Power-Up/Down Protection .40 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Electrical Specificatons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Revision History .54 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN 128Mb, 64Mb, 32Mb Q-FLASH MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. 3 ©2000 Micron Technology. Inc. ...
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... Figure 3: Pin and Ball Assignment Diagrams Figure 4: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Figure 5: Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Figure 6: Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Figure 7: Device Identifier Code Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 8: Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure 9: WRITE-to-BUFFER Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Figure 10: BYTE/WORD PROGRAM Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Figure 11: PROGRAM SUSPEND/RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Figure 12: BLOCK ERASE Flowchart ...
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... List of Tables Table 1: Pin/Ball Descriptions .10 Table 2: Chip-Enable Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Table 3: Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Table 4: Micron Q-Flash Memory Command Set Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Table 5: Summary of Query-Structure Output as a Function of Device and Mode . . . . . . . . . . . . . . . . . . . . . . .16 Table 6: Example: Query Structure Output of x16- and x8-Capable Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 1 Table 7: Query Structure ...
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... Additionally, the scalable command set (SCS) allows a single, simple software driver in all host sys- tems to work with all SCS-compliant Flash memory devices. The SCS provides the fastest system/device data transfer rates and minimizes the device and sys- tem-level implementation costs. ...
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... DQ9 36 DQ1 35 H CE2 DQ8 34 DQ0 BYTE# 30 A23 CE2 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. 7 128Mb, 64Mb, 32Mb Q-FLASH MEMORY 64-Ball FBGA A13 V A18 PEN CE0 A14 A25 A19 ...
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... CSN-11, “Product Mark/ Label,” at www.micron.com/csn. 8 128Mb, 64Mb, 32Mb Q-FLASH MEMORY Operating Temperature Range ET = Extended (-40ºC to +85ºC) Manufacturer’s Identification Code None = Intel (89h Micron (2Ch) Access Time ...
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... Q-FLASH MEMORY Input Buffer 128KB Memory Block (0) 128KB Memory Block (1) 128KB Memory Block (2) Write Buffer 128KB Memory Block (n-2) 128KB Memory Block (n-1) 128KB Memory Block ( Select Gates Sense Amplifiers Write/Erase-Bit Compare and Verify Query Output Buffer Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is either a WRITE to the command execution logic (CEL the memory array. Addresses and data are latched on the rising edge of the WE# pulse. CE0, CE1, Input Chip Enable: Three CE pins enable the use of multiple Flash devices CE2 in the system without requiring additional logic ...
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... CE0, CE1, CE2, OE#, WE#, and RP#. In system designs using multiple Q-Flash devices, CE0, CE1, and CE2 (CEx) select the memory device (see Table 2). To drive data out of the device and onto the I/O bus, OE# must be active and WE# must be inactive (V 09005aef80b5a323 MT28F640J3.fm – ...
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... Flash memory. During block erase, program, or lock bit configuration mode, automated Flash memories provide status information when accessed. When a CPU reset occurs with no Flash memory reset, proper initialization may not occur because the Flash memory may be providing status information instead of array data ...
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... DQ refers to DQ0–DQ7 if BYTE# is LOW and DQ0–DQ15 if BYTE# is HIGH. 4. High with an external pull-up resistor When Vpen £ Vpenlk, memory contents can be read, but not altered. Refer to the Recommended DC Electrical Char- acteristics table on page 43 can for control and address pins, and V ...
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... When the Vpen voltage is < Vpenlk, only READ operations from the status register, query, identifier codes, or blocks are enabled. Placing Vpenh on Vpen enables BLOCK ERASE, PROGRAM, and LOCK BIT Table 4: Micron Q-Flash Memory Command Set Definitions Note 1; notes appear on following page SCALABLE OR BASIC COMMAND ...
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... BA = Address within the block IA = Identifier code address; see Figure 7 on page 12 and Table 16 on page Query data base address PA = Address of memory location to be programmed Data read from identifier codes QD = Data read from query data base SRD = Data read from status register; see Table 17 on page 24 for a description of the status register bits PD = Data to be programmed at location PA ...
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... ASCII OFFSET CODE VALUE 10 0051 Q 11 0052 R 12 0059 Y 1 N/A Micron Technology, Inc., reserves the right to change products or specifications without notice. 16 128Mb, 64Mb, 32Mb Q-FLASH MEMORY QUERY DATA WITH BYTE ADDRESSING HEX HEX ASCII OFFSET CODE VALUE Null ...
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... Device code Block-specific information Reserved for vendor-specific information Reserved for vendor-specific information Command-set ID and vendor data offset Flash device layout Vendor-defined additional information specific to the primary vendor algorithm 17 128Mb, 64Mb, 32Mb Q-FLASH MEMORY BYTE ADDRESSING HEX CODE DQ7–DQ0 20h 51 21h 51 22h 52 ...
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... Alternate vendor command set and control interface ID code; 0000h means no second vendor-specified algorithm exists 19h 2 Secondary algorithm extended query table address; 0000h means none exists 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN 128Mb, 64Mb, 32Mb Q-FLASH MEMORY ADDRESS (BA+2)h (BA+2)h (BA+2)h ADDRESS 10h 11h 12h 13h ...
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... MT28F640J3.fm – Rev. N 3/05 EN 128Mb, 64Mb, 32Mb Q-FLASH MEMORY ADDRESS 1Bh 1Ch 1Dh 1Eh n 1Fh µs n 20h ...
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... Micron Technology, Inc., reserves the right to change products or specifications without notice. 20 128Mb, 64Mb, 32Mb Q-FLASH MEMORY CODE (see table 12 below) 27h 28h 02 x8/x16 29h 00 2Ah 05 32 2Bh 00 2Ch 01 1 2Dh 2Eh 2Fh 30h ...
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... PP Bits 0–3 BCD value in 100mV Bits 4–7 Hex value in volts NOTE: 1. The variable “P” pointer which is defined at CFI offset 15h. 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN 128Mb, 64Mb, 32Mb Q-FLASH MEMORY ADDRESS 31h 32h 33h 34h 35h 36h 37h ...
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... Reserved for future use. NOTE: 1. The variable “P” pointer which is defined at CFI offset 15h. 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN 128Mb, 64Mb, 32Mb Q-FLASH MEMORY ADDRESS 3Fh 40h ADDRESS 44h 45h 46h Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. Different ManID devices are ordered via separate part numbers. See Figure 4 on page 8 for details selects the specific block’s lock configuration code. See Figure 6 on page 11 for the device identifier code memory map. ...
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... PSLBS V PENS PENS 24 128Mb, 64Mb, 32Mb Q-FLASH MEMORY PSS DPS 2 1 NOTES Check STS or SR7 to determine block erase, program, or lock bit configuration completion. SR6–SR0 are not driven while SR7 = 0. If both SR5 and SR4 are “1s” after a block ...
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... BLOCK ERASE SUSPEND Command The BLOCK ERASE SUSPEND command allows block erase interruption in order to read or program data in another block of memory. Writing the BLOCK ERASE SUSPEND command immediately after starting the block erase process requests that the ISM suspend the block erase sequence at an appropriate point in the algorithm ...
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... When a BUFFERED WRITE is attempted while the corresponding block lock bit is set, SR1 and SR4 are set to “1.” RESERVED 6–0 STATUS REGISTER BITS 26 128Mb, 64Mb, 32Mb Q-FLASH MEMORY = BUFFERED WRITE is attempted PENH ≤ status register bits SR4 and SR3 PEN PENLK ...
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... SR1 and SR4 are set to “1.” PROGRAM SUSPEND Command The PROGRAM SUSPEND command enables pro- gram interruption to read data in other Flash memory locations. After starting the programming process, writing the PROGRAM SUSPEND command requests that the ISM suspend the program sequence at a pre- determined point in the algorithm ...
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... DQ5 DQ4 DQ3 RESERVED Used to control HOLD to a memory controller to prevent accessing a Flash memory subsystem while any Flash device’s ISM is busy. Used to generate a system interrupt pulse when any Flash device is an array has completed a BLOCK ERASE or sequence of queued BLOCK ERASEs; ...
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... CLEAR BLOCK LOCK BITS is required. PROTECTION REGISTER PROGRAM Command The 3V Q-Flash memory includes a 128-bit protec- tion register to increase the security of a system design. For example, the number contained in the pro- tection register can be used for the Flash component to communicate with other system components, such as the CPU or ASIC, to prevent device substitution ...
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... Q-FLASH MEMORY ...
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... Command complete. Write FFh after the last operation to reset the device to read array mode. Micron Technology, Inc., reserves the right to change products or specifications without notice. 31 128Mb, 64Mb, 32Mb Q-FLASH MEMORY WRITE-to- Data = E8h BUFFER Block Address XSR7 = Valid Addr = Block Address ...
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... Device Protect Error SR1 = 0 1 SR4 = Programming Error 0 Byte/Word Program Successful 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN 128Mb, 64Mb, 32Mb Q-FLASH MEMORY BUS OPERATION COMMAND WRITE SETUP BYTE/ WORD PROGRAM WRITE BYTE/WORD PROGRAM READ STANDBY Toggling OE# (LOW to HIGH to LOW) updates the status register. ...
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... BUS OPERATION WRITE READ STANDBY STANDBY WRITE READ Programming Completed WRITE Write FFh Read Data Array 33 128Mb, 64Mb, 32Mb Q-FLASH MEMORY COMMAND COMMENTS PROGRAM Data = B0h SUSPEND Addr = X Status Register Data Addr = X Check SR7 1 = ISM Ready 0 = ISM Busy Check SR6 1 = Programming Suspend ...
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... Full status check can be done after all erase and write sequences complete. Write FFh after the last operation to reset the device to read array mode. Micron Technology, Inc., reserves the right to change products or specifications without notice. 34 128Mb, 64Mb, 32Mb Q-FLASH MEMORY COMMENTS ERASE BLOCK Data = 20h Addr = Block Address ERASE ...
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... STANDBY WRITE BLOCK ERASE Completed Write FFh Read Data Array Micron Technology, Inc., reserves the right to change products or specifications without notice. 35 128Mb, 64Mb, 32Mb Q-FLASH MEMORY COMMAND COMMENTS ERASE SUSPEND Data = B0h Addr = X Status Register Data Addr = X Check SR7 1 = ISM Ready ...
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... If an error is detected, clear the status register before attempting retry or other error recovery. Error Micron Technology, Inc., reserves the right to change products or specifications without notice. 36 128Mb, 64Mb, 32Mb Q-FLASH MEMORY COMMAND COMMENTS SET BLOCK Data = 60h LOCK BITS Addr = Block Address ...
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... If an error is detected, clear the status register before attempting retry or other error recovery. Error BITS Error Micron Technology, Inc., reserves the right to change products or specifications without notice. 37 128Mb, 64Mb, 32Mb Q-FLASH MEMORY COMMAND COMMENTS CLEAR BLOCK Data = 60h LOCK BITS Addr = X ...
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... REGISTER command, in cases of multiple protection register Aborted program operations, before full status is checked error is detected, clear the status register before attempting retry or other error recovery. 38 128Mb, 64Mb, 32Mb Q-FLASH MEMORY COMMENTS PROTECTION Data = C0h PROGRAM SETUP PROTECTION Data = Data to Program ...
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... To efficiently use these control inputs, an address decoder should enable the device (see Table 2 on page 11) while OE# is connected to all memory devices and the system’s READ# control line. This ensures that only selected memory devices have active outputs while deselected memory devices are in standby mode ...
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... After block erase, program, or lock bit configura- tion, and after V transitions to V PEN must be placed in read array mode via the READ ARRAY command if subsequent access to the memory array is desired. During V transitions, V PEN kept at or below Power-Up/Down Protection During power transition, the device itself provides protection against accidental block erasure, program- ming, or lock bit configuration ...
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... Output shorted for no more than one second. No more than one output shorted at a time. 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN MIN -40 -65 -2. +0.5V which, during transitions, may overshoot Micron Technology, Inc., reserves the right to change products or specifications without notice. 41 128Mb, 64Mb, 32Mb Q-FLASH MEMORY MAX UNITS NOTES +85 °C +125 °C +5 100 mA ...
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... 0. BYTE# 32Mb 64Mb and 128Mb All other pins Micron Technology, Inc., reserves the right to change products or specifications without notice. 42 128Mb, 64Mb, 32Mb Q-FLASH MEMORY MIN MAX UNITS 2.7 3.6 V 2.7 3.6 V ±1 µA ±10 µA -0.5 0 0.5 ...
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... OUT CMOS inputs PEN CC TTL inputs PEN CC CMOS inputs PEN CC TTL inputs PEN CC Device is disabled 43 128Mb, 64Mb, 32Mb Q-FLASH MEMORY SYM DENSITY TYP MAX UNITS NOTES I 1 32Mb 75 120 CC 64Mb 75 128Mb 50 32Mb 100 2,000 64Mb 100 128Mb ...
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... TTL inputs are either CCR CCW (MAX) and V (MIN), or above V PENH . CC (MIN), or above V (MAX Q/2 Test Points 44 128Mb, 64Mb, 32Mb Q-FLASH MEMORY SYM DENSITY TYP MAX UNITS NOTES V All 0.8 PENLK V All 3.6 PENH V All 2.2 LKO or V with a minimum of -0.2V. ...
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... ODC All t ODO t All OH t All CB t All ABY t All ODB Micron Technology, Inc., reserves the right to change products or specifications without notice. 45 128Mb, 64Mb, 32Mb Q-FLASH MEMORY V = 2.7V–3. 2.7V–3.6V CC MIN MAX UNITS NOTES 110 ns 115 120 110 ns 115 120 110 ...
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... A SYMBOL DENSITY t All CWH t All APA t AOE applies. Non-array READs refer to status register READs, QUERY READs, Micron Technology, Inc., reserves the right to change products or specifications without notice. 46 128Mb, 64Mb, 32Mb Q-FLASH MEMORY V = 2.7V–3. 2.7V–3.6V CC MIN MAX UNITS NOTES 2.7V – ...
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... OH 115 120 ns t ABY ODB CWH 150 ns t APA 47 128Mb, 64Mb, 32Mb Q-FLASH MEMORY VALID VALID ADDRESS ADDRESS t CWH t ODC t ODO APA VALID VALID High-Z OUTPUT OUTPUT t ODB UNDEFINED V = 2.7V–3. 2.7V–3.6V CC MIN MAX 180 ...
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... VPH t WB and D for block erase, program, or lock bit configuration for any accesses after a WRITE. Micron Technology, Inc., reserves the right to change products or specifications without notice. 48 128Mb, 64Mb, 32Mb Q-FLASH MEMORY MAX UNITS NOTES µ ...
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... WED5 0.5 0.7 t WED6 LPS LES corner after 100,000 cycles. CC Micron Technology, Inc., reserves the right to change products or specifications without notice. 49 128Mb, 64Mb, 32Mb Q-FLASH MEMORY 128Mb 8 8 TYP MAX UNITS NOTES 180 654 µ 11.2 630 µs 4 0.7 1.7 sec 4 0 ...
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... WPH ns t VPS STS t ns VPH after a state machine operation. 50 128Mb, 64Mb, 32Mb Q-FLASH MEMORY Note 6 Note 7 VALID VALID READY SRD Note VPH UNDEFINED V = 2.7V–3. 2.7V–3.6V CC MIN MAX 200 ...
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... MT28F640J3.fm – Rev. N 3/05 EN ≤ +85ºC) A SYMBOL t PLPH t PHRH Figure 21: RESET Operation t PHRH t PLPH Micron Technology, Inc., reserves the right to change products or specifications without notice. 51 128Mb, 64Mb, 32Mb Q-FLASH MEMORY MIN MAX UNITS 35 µs 100 ns 4 ©2000 Micron Technology. Inc. NOTES ...
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... SEE DETAIL A 1.20 MAX Micron Technology, Inc., reserves the right to change products or specifications without notice. 52 128Mb, 64Mb, 32Mb Q-FLASH MEMORY PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PLATED LEAD FINISH: 90% Sn, 10% Pb, OR 100% Sn PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE 0.50 TYP 0.20 ± ...
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... C L 5.00 ±0.05 ® Micron Technology, Inc., reserves the right to change products or specifications without notice.. 53 128Mb, 64Mb, 32Mb Q-FLASH MEMORY 1.20 MAX BALL A1 ID MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE MATERIAL: PLASTIC LAMINATE SOLDER BALL MATERIAL: 62% Sn, 36% Pb 96.5% Sn, 3% Ag, 0.5% Cu SOLDER BALL PAD: Ø 0.33 NON SOLDER MASK DEFINED ...
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... MT28F640J3.fm – Rev and I 6 currents ODC, APA WH), STS, and 54 128Mb, 64Mb, 32Mb Q-FLASH MEMORY in Table 23 on page Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000 Micron Technology. Inc. ...
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... Added 128Mb device information • Added 64-ball FBGA (1.0mm pitch) package Original document, Rev. 1, Advance ............................................................................................................................12/00 09005aef80b5a323 MT28F640J3.fm – Rev. N 3/05 EN 128Mb, 64Mb, 32Mb Q-FLASH MEMORY Micron Technology, Inc., reserves the right to change products or specifications without notice. 55 ©2000 Micron Technology. Inc. ...