at17f080a ATMEL Corporation, at17f080a Datasheet

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at17f080a

Manufacturer Part Number
at17f080a
Description
8 Mbit In-system Programable Prom 3.3v Altera Pinout
Manufacturer
ATMEL Corporation
Datasheet

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Features
1. Description
The AT17FxxxA Series of In-System Programmable Configuration PROMs (Configu-
rators) provide an easy-to-use, cost-effective configuration memory for Field
Programmable Gate Arrays. The AT17FxxxA Series device is packaged in the 8-lead
LAP, 20-lead PLCC and 32-lead TQFP, see
figurator uses a simple serial-access procedure to configure one or more FPGA
devices.
The AT17FxxxA Series Configurators can be programmed with industry-standard pro-
grammers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1-1.
Package
8-lead LAP
20-lead PLCC
32-lead TQFP
Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
3.3V Output Capability
5V Tolerant I/O Pins
Program Support using the Atmel ATDH2200E System or Industry Third Party
Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera
Cyclone
Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
Low-power CMOS FLASH Process
Available in 8-lead LAP, 20-lead PLCC and 32-lead TQFP Packages
Emulation of Atmel’s AT24CXXX Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4 Bit Stream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33 MHz
Endurance: 5,000 Write Cycles Typical
Green (Lead/Halide-free/ROHS compliant) Packages
and APEX
AT17FxxxA Series Packages
Devices
AT17F040A
Yes
Yes
Yes
Table
1-1. The AT17FxxxA Series Con-
®
FLEX
®
, Excalibur
AT17F080A
Yes
Yes
Yes
, Stratix
®
,
FPGA
Configuration
Flash Memory
AT17F040A
AT17F080A
2823D–CNFG–2/08

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at17f080a Summary of contents

Page 1

... Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable. Table 1-1. AT17FxxxA Series Packages Package 8-lead LAP 20-lead PLCC 32-lead TQFP ® ® FLEX , Excalibur Table 1-1. The AT17FxxxA Series Con- AT17F040A AT17F080A Yes Yes Yes Yes Yes Yes FPGA ™ ® , Stratix , Configuration Flash Memory AT17F040A AT17F080A 2823D–CNFG–2/08 ...

Page 2

Pin Configuration PAGESEL1 RESET/OE AT17F040A/080A 2 8-lead LAP DATA 1 8 VCC DCLK 2 7 SER_EN RESET/ (A2) nCASC nCS 4 5 GND 20-lead PLCC DCLK PAGESEL1 7 15 ...

Page 3

Block Diagram Power-on READY Reset PAGE_EN Config. Page PAGESEL0 Select PAGESEL1 Flash Memory 4. Device Description The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface directly with the FPGA device control signals. All FPGA devices ...

Page 4

Pin Description Table 5-1. Name DATA DCLK PAGE_EN PAGESEL0 PAGESEL1 RESET/ nCS GND nCASC A2 READY SER_EN V CC (1) 5.1 DATA Three-state DATA output for FPGA configuration. Open-collector bi-directional pin for configura- tion programming. (1) 5.2 DCLK Three-state ...

Page 5

... This pin has an internal 20 k pull-up resistor. 2. This pin has an internal 30 kΩ pull-down resistor. AT17F040A/080A Table 5-2. When AT17F080A (8 Mbits) 00000 – 1FFFFh 20000 – 3FFFFh 40000 – 5FFFFh 60000 – 7FFFFh 00000 – 7FFFFh and GND is recommended. ...

Page 6

READY Open collector reset state indicator. Driven Low during power-up reset, released when power-up is complete. (recommended 4.7 kΩ pull-up on this pin if used). (1) 5.11 SER_EN The serial enable input must remain High during FPGA configuration operations. ...

Page 7

FPGA Master Serial Mode Summary The I/O and logic functions of any SRAM-based FPGA are established by a configuration pro- gram. The program is loaded either automatically upon power-up command, depending on the state of the FPGA ...

Page 8

... Exposure to Abso- lute Maximum Rating conditions for extended periods of time may affect device reliability. AT17FxxxA Series Configurator Min Max 2.97 3.63 2.97 3.63 AT17F040A AT17F080A Min Max Min 2 0.8 0 2.4 2.4 0.4 2 ...

Page 9

AC Characteristics nCS RESET/OE CLK T CE DATA 15. AC Characteristics when Cascading RESET/OE nCS CLK T DATA T nCASC 2823D–CNFG–2/08 T SCE CAC CDF LAST BIT T OCK OCE AT17F040A/080A T ...

Page 10

AC Characteristics Symbol Description ( Data Delay OE (2) T nCS to Data Delay CE (2) T DCLK to Data Delay CAC T Data Hold from nCS, OE, or DCLK OH (3) T nCS or OE ...

Page 11

... Min Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial θ [° C/W] JC θ (1) [° C/W] JA θ [° C/W] JC θ (1) [° C/W] JA AT17F040A/080A AT17F080A Max Min Max AT17F040A AT17F080A – – Units ...

Page 12

... Green Package Options (Pb/Halide-free/RoHS Compliant) Memory Size AT17F040A-30CU 4-Mbit AT17F040A-30JU AT17F080A-30CU 8-Mbit AT17F080A-30JU 8CN4 8-lead 1.04 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOIC Packages 20J 20-lead, Plastic J-leaded Chip Carrier (PLCC) 32A 32-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP) ...

Page 13

Packaging Information 20.1 8CN4 – LAP Marked Pin1 Indentifier E Top View 0.10 mm TYP Bottom View Note: 1. Metal Pad Dimensions. 2. All exposed metal area shall have the following finished platings. ...

Page 14

PLCC 1.14(0.045) X 45˚ B 0.51(0.020)MAX 45˚ MAX (3X) Notes: 1. This package conforms to JEDEC reference MS-018, Variation AA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. ...

Page 15

TQFP PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 ...

Page 16

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. Atmel Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia ...

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