mxd1005 Maxim Integrated Products, Inc., mxd1005 Datasheet

no-image

mxd1005

Manufacturer Part Number
mxd1005
Description
Mxd1005 5-tap Silicon Delay Line
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
The MXD1005 silicon delay line offers five equally
spaced taps with delays ranging from 12ns to 250ns
and a nominal accuracy of ±2ns or ±3%, whichever is
greater. Relative to hybrid solutions, this device offers
enhanced performance and higher reliability, and
reduces overall cost. Each tap can drive up to ten 74LS
loads.
The MXD1005 is available in multiple versions, each
offering a different combination of delay times. It comes
in the space-saving 8-pin µMAX package, as well as an
8-pin SO or DIP, allowing full compatibility with the
DS1005 and other delay line products.
________________________Applications
19-1309; Rev 0; 10/97
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
_________________Pin Configurations
_______________General Description
Pin Configurations continued at end of data sheet.
TOP VIEW
Clock Synchronization
Digital Systems
TAP2
TAP4
TAP2
TAP4
GND
GND
N.C.
N.C.
N.C.
IN
IN
________________________________________________________________ Maxim Integrated Products
1
2
4
1
2
3
4
5
6
7
3
DIP/SO/ MAX
MXD1005
MXD1005
DIP
14
13
12
11
10
6
8
7
5
9
8
V
TAP1
TAP3
TAP5
N.C.
V
N.C.
TAP1
N.C.
TAP3
TAP5
CC
CC
5-Tap Silicon Delay Line
* Dice are tested at T
Note: To complete the ordering information, fill in the blank with
the part number extension from the Part Number and Delay
Times table to indicate the desired delay per output.
____________________________Features
_____Part Number and Delay Times
Note: Contact factory for characterization data.
Functional Diagram appears at end of data sheet.
______________Ordering Information
MXD1005C/D__
MXD1005PA__
MXD1005PD__
MXD1005SA__
MXD1005SE__
MXD1005UA__
(MXD1005_ _ __)
PART NUMBER
Improved Second Source to DS1005
Available in Space-Saving 8-Pin µMAX Package
17mA Supply Current vs. Dallas’ 40mA
Low Cost
Delay Tolerance of ±2ns or ±3%, whichever is
Greater
TTL/CMOS-Compatible Logic
Leading- and Trailing-Edge Accuracy
Custom Delays Available
EXTENSION
PART
100
125
150
175
200
250
60
75
A
= +25°C.
TAP1
DELAY (t
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
TEMP. RANGE
12
15
20
25
30
35
40
50
0°C to +70°C
TAP2
100
PHL
24
30
40
50
60
70
80
TAP4
, t
PLH
TAP3
105
120
150
36
45
60
75
90
) PER OUTPUT (ns)
Dice*
8 Plastic DIP
14 Plastic DIP
8 SO
16 Narrow SO
8 µMAX
PIN-PACKAGE
TAP4
100
120
140
160
200
48
60
80
TAP5
100
125
150
175
200
250
60
75
1

Related parts for mxd1005

mxd1005 Summary of contents

Page 1

... Each tap can drive up to ten 74LS loads. The MXD1005 is available in multiple versions, each offering a different combination of delay times. It comes in the space-saving 8-pin µMAX package, as well as an 8-pin SO or DIP, allowing full compatibility with the DS1005 and other delay line products ...

Page 2

... Note 2: All voltages referenced to GND. Note 3: Measured with outputs open. Note function of frequency and TAP5 delay. Only an MXD1005_ _60 operating with a 40ns period and V CC have a maximum I of 70mA. For example, an MXD1005_ _100 will not exceed 30mA. See Supply Current vs. Input CC Frequency graph in Typical Operating Characteristics ...

Page 3

... T = +25°C, unless otherwise noted ACTIVE CURRENT vs. FREQUENCY 18 50% DUTY CYCLE MXD1005_ _75 11 MXD1005_ _200 10 0.001 0.01 0.1 FREQUENCY (MHz) MXD1005_ _100 TO MXD1005_ _200 PERCENT CHANGE IN DELAY vs. TEMPERATURE 2.0 1.5 1.0 0.5 t PHL 0 -0.5 t PLH -1.0 -1.5 RELATIVE TO NOMINAL (+25°C) -2.0 -40 - TEMPERATURE (°C) ...

Page 4

Silicon Delay Line ______________________________________________________________Pin Description PIN 8-PIN 14-PIN DIP 16-PIN SO DIP/SO/µMAX 11 10, — ...

Page 5

... OUT Figure 1. Timing Diagram __________Applications Information Supply and Temperature Variations in supply voltage may affect the MXD1005’s fixed tap delays. Supply voltages beyond the specified range may result with larger variations. The devices are internally compensated to reduce the effects of temper- ature variations. Although these devices might vary with ...

Page 6

... Silicon Delay Line _________________________________________________________Functional Diagram 20% IN ____Pin Configurations (continued) TOP VIEW N. N. MXD1005 4 TAP2 13 N. TAP4 GND _______________________________________________________________________________________ TAP1 TAP2 TAP3 20% 20% MXD1005 ___________________Chip Information TRANSISTOR COUNT: 824 V CC N.C. N.C. TAP1 N.C. TAP3 N.C. TAP5 TAP4 TAP5 20% 20% ...

Page 7

Information _______________________________________________________________________________________ 5-Tap Silicon Delay Line 7 ...

Page 8

Silicon Delay Line ___________________________________________Package Information (continued) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and ...

Related keywords