stc3800 Connor-Winfield VCXOs, stc3800 Datasheet
stc3800
Related parts for stc3800
stc3800 Summary of contents
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... INTEGRATED - STRATUM 3E Description 2111 Comprehensive Drive The STC3800 is an integrated single chip Aurora, Illinois 60505 solution for the Synchronous Timing Source Phone: 630- 851- 4722 in SONET/SDH network elements. The Fax: 630- 851- 5040 device generates four synchronous clocks, www.conwin.com including BITS, and is fully compliant with Telcordia GR-1244-CORE, GR-253-CORE and ITU-T G ...
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... Performance Definitions ................................................................................................ 26 Jitter and Wander Fractional Frequency Offset and Drift Time Interval Error (TIE) Maximum Time Interval Error (MTIE) Time Deviation (TDEV) STC3800 performance .............................................................................................. 26-29 Input Jitter Tolerance Input Wander Tolerance Phase Transient Tolerance Free Run Frequency Accuracy Hold Over Frequency Stability ...
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... Note: Pins indicated as “MNC” are mandatory no-connects. Pins indicated as “NC” may be left uncon- nected or may be grounded. Preliminary Data Sheet #: TM061 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved STC3800 Pin Diagram (Top View) Figure AD2 ...
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Pin Name Pin # Vdd2.5 A8, C4, E1, E10, H1, H5, H12 J7 Vdd3.3 E4, E6, E7, E9, H10, J3, L5, M10 GND A6, B2, B11, F5, F6, F7, F10, G2, G5, G6, G7, K7, K10, L1 AVdd2.5 E8, G3 ...
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Pin Name Pin # Sel0 A9 Sel1 A10 Sel2 A11 Sel3 A12 BITS_Sel C11 LOS H2 LOL J2 Hold_Avail K2 Xref K1 Ref1 M1 Ref2 M2 Ref3 M3 Ref4 M4 Ref5 M5 Ref6 M6 Ref7 M7 Ref8 M8 Sync_Clk G12 ...
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Absolute Maximum Ratings Table 2 Symbol Parameter Vdd2.5 Logic power supply voltage, 2.5V Vdd3.3 Logic power supply voltage 3.3V AVdd2.5 Analog power supply voltage, 2.5V V Logic input voltage, rel. to GND IN T Storage Temperature STG Note 1: Stresses ...
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Register Map continued Table 4 Address Reg Name 0x06 Max_Pullin_Range 0x07 Xref_Activity 0x08 Ref_Activity 0x09 Ref_Pullin_Sts 0x0a Ref_Qualified 0x0b Ref_Mask 0x0c Ref_Available 0x0d Ref_Rev_Delay 0x0e MS_Phase_Offset 0x0f Calibration 0x10 Fr_Pulse_Width 0x11 DPLL_Status 0x12 Intr_Event 0x13 Intr_Enable 0x14 Ref1_Frq_Offset 0x15 Ref2_Frq_Offset ...
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... Detailed Description The STC3800 is a single chip synchronization and timing solution for the Stratum 3 and 3E Synchronous Equipment Timing Source (SETS) function in network elements. Its highly integrated design includes hardware and firmware to implement all of the necessary reference selection, monitoring, digital filtering, synthesis, and control functions. An external OCXO/TCXO, DAC, and VCXO (and optional EEPROM) complete a system level solution (see Functional Block Diagram) ...
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... When a new reference is acquired, maximum frequency slew limits ensure smooth frequency changes. Once lock is achieved, (<100 seconds for stratum 3, <700 seconds for stratum 3E), the “Locked” bit is set. If the STC3800 is unable to maintain lock, Loss of Lock (LOL) is asserted. All transitions between locked, Hold Over and Free Run modes are performed with no phase hit and smooth frequency and phase transitions ...
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... Detailed Description continued Master/Slave Operation Pairs of STC3800 devices may be operated in a master/slave configuration for added reliability. A typical configuration is shown below: Ref In Ref In The Sync_8K or Sync_Clk output of each device is cross-connected to the other device’s Xref input. The device auto- detects the frequency on the Xref input. Master or slave state of a device is determined by the M/ S pin. Thus, master/ slave state is always manually controlled by the application ...
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... Detailed Description continued Control Modes Parallel or serial bus interfaces are provided to access STC3800 internal control and status registers.The selected reference, operational modes can be accessed from either the bus interface or external device pins. Master/slave mode can only be controlled by M/S pin. Hardware Control – The device may be configured for direct pin control over key functions for simple hardwired configurations. The HM_Ref pin enables hardware control of reference selection and operational mode. When “ ...
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Detailed Description continued Register Control – Bus/Register access is available in 8-bit parallel or SPI form, as selected by the Bmode pin. Bmode=1 selects parallel bus access, and Bmode=0 selects SPI. Parallel bus and SPI data I/O operations are shown ...
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Detailed Description continued SCLK t t RWs RWh SDI A0 A1 LSB SDO SCLK t t RWs RWh A0 A1 SDI LSB Symbol Parameter low to SCLK ...
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Detailed Description continued Reference Input Quality Monitoring Each reference input is monitored for signal presence and frequency offset. Signal presence for the Ref1-8 inputs is indicated in the Ref_Activity register and signal presence and frequency for the Xref input is ...
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Detailed Description continued The automatic reference selection is shown in the following state diagram: Priority of Ref n > Ref m Ref_Rev_Delay Locked on Ref n The operational mode is according to the following state diagram: Higher priority Ref return ...
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... Sync_8K kHz output available as a frame reference or may be used as a synchronization signal for cross- coupled pairs of STC3800 devices operated in master/slave mode. Sync_8K may be a 50% duty cycle signal, or variable high-going pulse width, as determined by the Ctl_Mode and Fr_Pulse_Width registers. In variable pulse width mode, the width may be from multiples of the Sync_Clk cycle time ...
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Detailed Description continued Interrupts Eight interrupts are provided and appear in the INTR_EVENT (0x12) register. Each interrupt can be individually enabled or disabled via the INTR_ENABLE (0x13) register. Each bit enables or disables the corresponding interrupt from asserting the SPI_INT ...
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Register Descriptions and Operation Chip_ID_low, 0x00 (R) Low byte of chip ID: 0x11 Chip_ID_High, 0x01 (R) High byte of chip ID: 0x30 Chip_Revision, 0x02 (R) Chip revision number: Chip revision number is subject to change. Bandwidth_PBO, 0x03 (R/W) Bit 7 ...
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Register Descriptions and Operation continued Op_Mode, 0x05 (R/W) Bit 7 ~ Bit 5 Reserved When HM_Ref = 1, enabling hardware control of reference selection and operational mode control, bits this register are read-only and reflect the ...
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Register Descriptions and Operation continued Ref_Pullin_Sts, 0x09 (R) Bit 7 Bit 6 ref8 sts ref7 sts ref6 sts 1: in range 1: in range 1: in range 0: out range 0: out range 0: out range Each bit indicates if ...
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... MS_Phase_Offset register, to compensate for the path length of the Sync_8K or Sync_Clk to Xref connection phase offset is used, then the two STC3800 devices would typically be written to the appropriate phase offset values for the respective path lengths of each Sync_8K or Sync_Clk to Xref connection, to ensure that the same relative output signal phases will persist through master/slave switches ...
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Register Descriptions and Operation continued Intr_Event, 0x12 (R) Bit 7 Bit 6 Bit 5 Loss of Loss of Active Lock Signal reference change Interrupt state = 1. When an enabled interrupt occurs, the INTR pin is asserted, active low. All ...
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Register Descriptions and Operation continued Ref(1-8)_Frq_Priority, 0x1c ~ 0x23 (R/W) Bit 7 ~ Bit 4 Frequency 0000: None 0001: 8 kHz 0010: 1.544 MHz 0011: 2.048 MHz 0100: 12.96 MHz 0101: 19.44 MHz 0110: 25.92 MHz 0111: 38.88 MHz 1000: ...
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Register Descriptions and Operation continued History_Cmd, 0x26 (R/W) Bit 7 ~ Bit 2 Reserved Bits 0-1 are written to save a Hold Over history to the backup history, restore the active Hold Over history from the backup, or flush the ...
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Register Descriptions and Operation continued Chksum, 0x33 (R) Bit 7 ~ Bit 1 Reserved Checksum verification register for configuration data. See Application Notes, Configuration Data section. Initialized to zero on power-up/reset, indicates 0 = fail pass upon ...
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... Input jitter tolerance is the amount of jitter at its input a clock can tolerate before generating an indication of improper operation. GR-1244 and ITU-813 requirements specify jitter amplitude v.s. jitter frequency for jitter tolerance. The STC3800 device provides jitter tolerance that meets the specified requirements. Input Wander Tolerance – ...
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... STC3800 in the application section will meet GR-1244 and ITU G.813 requirements. Wander Generation – Wander generation is the process whereby wander appears at the output of a clock in the absence of input wander. The STC3800 wander generation characteristics, MTIE and TDEV, are shown below, along with the requirements masks (bandwidth = 0.39 Hz): 1000 ...
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... Jitter Broadband 500 Hz - 1.3 MHz 65 kHz - 1.3 MHz Jitter Transfer – Jitter transfer is the degree to which input jitter is attenuated (or amplified) from input to output of a clock function of the selected bandwidth. The STC3800 jitter transfer characteristics are shown below -10 dB -15 dB fc=0 ...
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... Capture Range and Lock Range within which the phase locked loop is able to achieve lock and hold lock, respectively. The STC3800 stratum 3 performance is shown below: Characteristic Capture range Lock in range This is the minimum chip capability, and guarantees the ability to capture and lock with a reference that is offset the maximum allowed in one direction in the presence of an OCXO/TCXO that is offset the maximum in the opposite direction (4 ...
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... Application Notes This section describes typical application use of the STC3800 device. The General section applies to all application variations, while the remaining sections detail use depending on the level of control and automatic operation the application desires. General Power and Ground – Well-planned noise-minimizing power and ground are essential to achieving the best performance of the device ...
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... Analog ground “0” = PECL “1” = TTL (x) Number of pins “0” = Bus Config. Data from: “1” = EEPROM Figure 9 Vdd3.3 (8) STC3800 Vdd2.5 (8) AVdd2.5 (2) VC_Sel Dmode GND (14) Preliminary Data Sheet #: TM061 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved .1uF ceramic ...
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... For some applications, reliability requirements may demand that the clock system to be duplicated. The STC3800 device will support the master/slave duplicated configuration for such applications. To facilitate it’s use, the device includes the necessary signal cross coupling and control functions. Redundancy for reliability implies two major considerations: 1) Maintaining separate failure groups such that a failure in one group does not affect it’ ...
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... The path lengths of the two Sync_8K or Sync_Clk to Xref signals is of interest, however. They need not be the same. However, to accommodate path length delays, the STC3800 provides a programmable phase skew feature, which allows the application to offset the output clocks from the cross-reference signal ± 32 ns, in 0.25nS increments. ...
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Application Notes continued Master/Slave Operation and Control Master or slave state of a device is determined by the M/S pin. Choosing the master/slave states is a function of the application, based on the configuration of the rest of the system ...
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Application Notes continued Configuration Data – Following any device reset, either via power-up or operation of the Reset pin, the device needs to be loaded with its DPLL configuration data. This data may come from either an external EEPROM, or ...
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... EEPROM Access Architecture Figure 11 EE_Page_Num Register Address/Control Read/Write Control EE_Wrt_Mode EE_Cmd Registers 32 Byte FIFO EE_FIFO_Port Register STC3800 Preliminary Data Sheet #: TM061 © Copyright 2001 The Connor-Winfield Corp. All Rights Reserved EEPROM 32 Bytes Page 0 32 Bytes Page 1 Data . . . 32 Bytes Page 231 Page ...
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Application Notes continued Hold Over History Accumulation and Maintenance controlled in greater detail if register bus access to the device is provided. Hold Over history accumulation and control encompasses three device internal registers, three bus access registers for control and ...
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Application Notes continued Reference Switch Reference Switch History bulid complete Reference Lock (with “Continue” set) Reference Switch Reference Switch History restored from backup, re-start the building procedure Hold Over History and Status States Figure 12 Reset Acquire Reference Hold Complete ...
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... Hold Over state. Boundary Scan – The STC3800 provides a standard IEEE 1149.1 JTAG boundary scan interface via the TMS, TCK, TDI, TDO, and TRST pins. Boundary scan may be used to verify proper device I/O connectivity and functionality. ...
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... Application Notes continued Control Modes The STC3800 device may be controlled and interfaced in a pure hardware mode with pin signals, or via SPI or parallel bus/register access. With register access, the device can in turn be operated in a manual control mode, or automatic control and reference selection mode. Hardware mode is most suitable for simple environments where minimal external intelligence is desired ...
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Application Notes continued Sel0-3 - Write to the appropriate values for the desired reference selection and operating mode, as shown below: (Note: Reference switches are performed in a hitless manner. However, if the application externally changes the frequency of a ...
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... Parallel bus operation uses CS, ALE, R/W, RDY, and AD0-7, as described in the Register Control section, Figures 3 and 4, and Table 6. SPI uses CS, SCLK, SDI, and SDO, as described in the Register Control section, Figures 5 and 6, and Table 7. Register Access Manual Control Interfaces Figure 14 STC3800 Reset BITS_Sel HM_Ref Bmode ...
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Application Notes continued Set the device bandwidth and enable/disable phase build-out by writing the appropriate values to the Bandwidth_PBO register, 0x03. (See Register Descriptions and Operation). The recommended value is .098 Hz for Stratum 3 and 0.77 MHz for Stratum ...
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Application Notes continued Select the desired operational mode and reference by writing the appropriate value to register Op_Mode (0x05). (Note: Reference switches are performed in a hitless manner. However, if the application externally changes the frequency of a particular reference, ...
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Application Notes continued Register Access Automatic Control For Register Access Automatic Control, the interfaces, reset, and bus operations are the same as shown in Figure 13 and described in the Register Access Manual Control section. The Bandwidth_PBO register write operation ...
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Application Notes continued Max_Pullin_Range register (0x06) - Set to the maximum allowed frequency offset for a reference. Automatic reference selection is accompanied by per-reference selectable priorities. These are written to bits 2-0 of the Ref(1-8)_Frq_Priority registers. The highest priority is ...
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Mechanical Specifications A1 Ball Pad Corner 0.70 mm [0.03"] 0.35 mm [0.01"] Additional External Components 1. Place series resistors (33 ohms) on all reference inputs. 2. Place series resistors (33 ohms) on SPI_IN and SPI_CLK inputs. 3. Place one .01uF ...
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Revision Revision Date Note A02 07/01/03 Advance Release P02 01/21/04 Miscellaneous Spec Revisions P03 02/09/04 Features: GR-253-CORE, 10 P04 02/19/04 External Components, PCB Layout Rec, JTAG/ISP P05 11/15/04 EEPROM Access Architecture P06 11/22/04 Chip Revision Update - ppb, ...