stm8af6166t STMicroelectronics, stm8af6166t Datasheet
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stm8af6166t Summary of contents
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Automotive 8-bit MCU, with up to 128 Kbytes Flash, EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I² 5.5 V Features Core ■ Max MHz CPU ■ Advanced STM8 core with Harvard ...
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Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM8AF61xx, STM8AF51xx 6 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM8AF61xx, STM8AF51xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures List of figures Figure 1. STM8 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM8AF61xx, STM8AF51xx 1 Introduction This datasheet contains the description of the STM8AF61xx/STM8AF51xx family features, pinout, electrical characteristics, mechanical data and ordering information. ● For complete information on the STM8A microcontroller memory, registers and peripherals, please refer to the STM8S/STM8A reference ...
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Description 2 Description The STM8AF51xx and STM8AF61xx automotive 8-bit microcontrollers offer from 16 Kbytes up to 128 Kbytes of program memory and integrated true data EEPROM. The STM8AF51xx series features a CAN interface. All devices of the STM8A product line ...
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STM8AF61xx, STM8AF51xx 3 Product line-up Table 2. STM8A common features Order code STM8 CPU Single-wire ICP/ICD interface Nested interrupts: 32 vectors, 3 software priority levels Program memory read-out protection STMA8AF51xx Window watchdog and standard watchdog timers STMA8AF61xx Auto wake-up timer ...
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... K STM8AF61A8T 128 K STM8AF6198T 96 K STM8AF6188T 64 K LQFP48 (1) (7x7) STM8AF6178T 48 K STM8AF6168T 32 K STM8AF6148T 16 K STM8AF6186T 64 K STM8AF6176T 48 K LQFP32 STM8AF6166T 32 K (7x7) STM8AF6146T Also QFN package available 10/84 RAM Data EE 10-bit (bytes) (bytes) A/D ch. (IC/OC/PWM ...
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STM8AF61xx, STM8AF51xx 4 Block diagram Figure 1. STM8 device block diagram Reset Single wire debug interf. Master/slave autosynchro 400 Kbit/s 8 Mbit/s LIN master SPI emul. 1 Mbit/s 16 channels Reset block Clock controller Reset Detector POR PDR Clock to ...
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Product overview 5 Product overview The following section intends to give an overview of the basic features of the STM8A functional modules and peripherals. For more detailed information please refer to the STM8 hardware reference manual RM0009. 5.1 Central processing ...
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STM8AF61xx, STM8AF51xx SWIM Single wire interface for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. There is a maximum data transmission speed of 145 bytes/ms. Debug module The non-intrusive ...
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Product overview Write protection (WP) Write protection in application mode is intended to avoid unintentional overwriting of the memory in case of user software malfunction. The implemented WP scheme enables ● Write protection of the program memory in user mode ...
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STM8AF61xx, STM8AF51xx Speed ● Operation MHz CPU clock frequency without wait-states ● Programming time (same for word or block): – Fast programming (without erase): < – Standard programming (erase + program): < ...
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Product overview 5.5.1 Internal 16 MHz RC oscillator ● Default clock after reset 2 MHz (16 MHz/8) ● Wake-up time: < 2 µs Precision: ● Calibration during final test at room-temperature to ±1 % ● ± 4.5 to ...
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STM8AF61xx, STM8AF51xx 5.5.5 Clock security system (CSS) The clock security system protects against a system stall in case of an external crystal clock failure. In case of a clock failure an interrupt is generated and the high speed internal clock ...
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Product overview 5.6.3 Multipurpose and PWM timers The STM8 devices contain up to three 16-bit multipurpose and PWM timers providing 9 CAPCOM channels in total. Table 5. STM8 timer configuration Timer Timer1 Timer2 Timer3 Timer4 16-bit PWM timers ● 16-bit ...
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STM8AF61xx, STM8AF51xx 5.7 ADC All STM8 products contain one 10-bit successive approximation ADC with multiplexed input channels. General features: ● Input voltage range ● Conversion time: 14 clock cycles (7 µ MHz ...
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Product overview Asynchronous communication (SCI) ● Full duplex communication - NRZ standard format (mark/space) ● Programmable transmit and receive baud rates Mbit/s (f following any standard baud rate regardless of the input frequency ● Separate enable bits ...
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STM8AF61xx, STM8AF51xx Asynchronous communication (SCI) ● Full duplex, asynchronous communications - NRZ standard format (mark/space) ● Independently programmable transmit and receive baud rates up to 500 Kbit/s ● Programmable data word length ( bits) ● Low-power standby mode ...
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Product overview 5.8.5 CAN The beCAN3 controller (basic enhanced CAN), interfaces the CAN network and supports the CAN protocol version 2.0A and B. It has been designed to manage a high number of incoming messages efficiently with a minimum CPU ...
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STM8AF61xx, STM8AF51xx 5.9 Input/output specifications The product features four different I/O types: ● Standard I/O 1.5 mA, rise/fall time 120 load, 2 MHz ● Fast I/O 3 mA, rise/fall time ...
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Pinouts and pin description 6 Pinouts and pin description 6.1 LQFP package pinouts Figure 3. LQFP 80-pin pinout NRST OSCIN/PA1 OSCOUT/PA2 V SSIO_1 V SS VCAP DDIO_1 TIM2_CC3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 (HS) PH0 HS) PH1 ( PH2 ...
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STM8AF61xx, STM8AF51xx Figure 4. LQFP 64-pin pinout OSCIN/PA1 OSCOUT/PA2 TIM2_CC3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 1. Only available on the STM8AF51xx product line NRST 1 2 ...
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Pinouts and pin description Figure 5. LQFP 48-pin pinout 1. Only available on the STM8AF51xx product line 26/ NRST 1 OSCIN/PA1 2 OSCOUT/PA2 SSIO_1 V ...
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STM8AF61xx, STM8AF51xx Figure 6. LQFP 32-pin pinout 6.2 Pin description Table 6. Legend/abbreviation for Type Level Output speed Port and control configuration Reset state is shown in bold NRST 1 OSCIN/PA1 2 ...
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Pinouts and pin description Table 7. STM8A MCU family pin description Pin number Pin name NRST PA1/OSCIN PA2/OSCOUT SSIO_1 ...
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STM8AF61xx, STM8AF51xx Table 7. STM8A MCU family pin description (continued) Pin number Pin name PB7/AIN7 PB6/AIN6 PB5/AIN5 PB4/AIN4 PB3/AIN3 32 ...
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Pinouts and pin description Table 7. STM8A MCU family pin description (continued) Pin number Pin name PC4/TIM1_CC4 PC5/SPI_SCK SSIO_2 DDIO_2 50 41 ...
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STM8AF61xx, STM8AF51xx Table 7. STM8A MCU family pin description (continued) Pin number Pin name PD0/TIM3_CC2 PD1/SWIM PD2/TIM3_CC1 PD3/TIM2_CC2 PD4/TIM2_CC1 EEP ...
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Memory map 7 Memory map Figure 7. STM8A products - register and memory map 0000h - 17FFh Kbytes RAM 1800h - 3FFFh Reserved 4000h - 47FFh Kbytes data EE 4800h - 487Fh 128 user ...
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STM8AF61xx, STM8AF51xx 8 Interrupt table Table 8. Interrupt table Source Priority block - Reset - TRAP 0 TLI 1 AWU Clock 2 controller 3 MISC 4 MISC 5 MISC 6 MISC 7 MISC 8 CAN 9 CAN 10 SPI 11 ...
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Interrupt table Table 8. Interrupt table (continued) Source Priority block Simple 21 USART (SCI2) 22 ADC Very-low- 23 end timer (timer 4) 24 EEPROM 34/84 Interrupt vector Description address Receive data full reg. 805Ch End ...
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STM8AF61xx, STM8AF51xx 9 Register mapping Table 9. I/O port hardware register map Address Block 00 5000h 00 5001h 00 5002h Port A 00 5003h 00 5004h 00 5005h 00 5006h 00 5007h Port B 00 5008h 00 5009h 00 500Ah ...
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Register mapping Table 9. I/O port hardware register map (continued) Address Block 00 501Eh 00 501Fh 00 5020h Port G 00 5021h 00 5022h 00 5023h 00 5024h 00 5025h Port H 00 5026h 00 5027h 00 5028h 00 5029h ...
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STM8AF61xx, STM8AF51xx Table 10. General hardware register map Address Block 00 5050h to 00 5059h 00 505Ah 00 505Bh 00 505Ch Flash 00 505Dh 00 505Eh 00 505Fh 00 5060h to 00 5061h 00 5062h Flash 00 5063h 00 5064h ...
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Register mapping Table 10. General hardware register map (continued) Address Block 00 50C3h 00 50C4h 00 50C5h 00 50C6h 00 50C7h CLK 00 50C8h 00 50C9h 00 50CAh 00 50CBh 00 50CCh 00 50CDh 00 50CEh to 00 50D0h 00 ...
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STM8AF61xx, STM8AF51xx Table 10. General hardware register map (continued) Address Block 00 5200h 00 5201h 00 5202h 00 5203h SPI 00 5204h 00 5205h 00 5206h 00 5207h 00 5208h to 00 520Fh 00 5210h 00 5211h 00 5212h 00 ...
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Register mapping Table 10. General hardware register map (continued) Address Block 00 5230h 00 5231h 00 5232h 00 5233h 00 5234h 00 5235h USART 00 5236h 00 5237h 00 5238h 00 5239h 00 523Ah 00 523Bh to 00 523Fh 00 ...
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STM8AF61xx, STM8AF51xx Table 10. General hardware register map (continued) Address Block 00 5250h 00 5251h 00 5252h 00 5253h 00 5254h 00 5255h 00 5256h 00 5257h 00 5258h 00 5259h 00 525Ah 00 525Bh 00 525Ch 00 525Dh 00 ...
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Register mapping Table 10. General hardware register map (continued) Address Block 00 5300h 00 5301h 00 5302h 00 5303h 00 5304h 00 5305h 00 5306h 00 5307h 00 5308h 00 5309h 00 530Ah TIM2 00 530Bh 00 530Ch 00 530Dh ...
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STM8AF61xx, STM8AF51xx Table 10. General hardware register map (continued) Address Block 00 5320h 00 5321h 00 5322h 00 5323h 00 5324h 00 5325h 00 5326h 00 5327h 00 5328h TIM3 00 5329h 00 532Ah 00 532Bh 00 532Ch 00 532Dh ...
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Register mapping Table 10. General hardware register map (continued) Address Block 00 5400h 00 5401h 00 5402h 00 5403h ADC 00 5404h 00 5405h 00 5406h 00 5407h 00 5408h to 00 541Fh 00 5420h 00 5421h 00 5422h 00 ...
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STM8AF61xx, STM8AF51xx Table 10. General hardware register map (continued) Address Block 00 542Ch 00 542Dh 00 542Eh 00 542Fh 00 5430h 00 5431h CAN 00 5432h 00 5433h 00 5434h 00 5435h 00 5436h 00 5437h 00 5438h to 00 ...
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Register mapping Table 11. CPU/SWIM/debug module/interrupt controller registers Address Block 00 7F00h 00 7F01h 00 7F02h 00 7F03h 00 7F04h 00 7F05h CPU 00 7F06h 00 7F07h 00 7F08h 00 7F09h 00 7F0Ah 00 7F0Bh to 00 7F5Fh 00 7F60h ...
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STM8AF61xx, STM8AF51xx Table 11. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block 00 7F90h 00 7F91h 00 7F92h 00 7F93h 00 7F94h 00 7F95h DM 00 7F96h 00 7F97h 00 7F98h 00 7F99h 00 7F9Ah 00 7F9Bh to 00 7F9Fh Register ...
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Option bytes 10 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Except for the ROP (read-out protection) byte, each ...
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STM8AF61xx, STM8AF51xx Table 13. Option byte description Option byte no. OPT0 OPT1 OPT2 Description ROP[7:0] Memory readout protection (ROP) AAh: Enable readout protection (write access via SWIM protocol) Note: Refer to the STM8S/STM8A Reference manual RM0009 section on Flash/EEPROM memory ...
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Option bytes Table 13. Option byte description (continued) Option byte no. OPT3 OPT4 OPT5 OPT6 OPT7 50/84 Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI clock is available as ...
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STM8AF61xx, STM8AF51xx 11 Electrical characteristics 11.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 11.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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Electrical characteristics Figure 9. Pin input voltage 11.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these ...
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STM8AF61xx, STM8AF51xx Table 15. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...
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Electrical characteristics 11.3 Operating conditions Table 17. General operating conditions Symbol f Internal CPU clock frequency CPU V V Standard operating voltage DD/ DD_IO Junction temperature range J Table 18. Operating conditions at power-up/power-down Symbol Parameter V ...
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STM8AF61xx, STM8AF51xx 11.3.1 Supply current characteristics Total current consumption The MCU is placed under the following conditions: ● All I/O pins in input mode with a static value at V ● All peripherals are enabled except if explicitly mentioned. Subject ...
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Electrical characteristics Table 22. Total current consumption and timing in halt, fast active halt and slow active halt modes at V Symbol Parameter Supply current in I DD(H) halt mode Supply current in I fast active halt DD(FAH) mode Supply ...
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STM8AF61xx, STM8AF51xx Figure 10. External clock source V HSEH V HSEL External clock source HSE crystal/ceramic resonator oscillator The HSE clock oscillator can be supplied with a 1-24 MHz crystal/ceramic resonator oscillator.All the information given in this paragraph is based ...
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Electrical characteristics Figure 11. HSE oscillator circuit diagram HSE oscillator critical g ( × Π × mcrit R : Notional resistance (see crystal specification) m Co: Shunt capacitance (see crystal specification) C: Grounded external capacitance g >> ...
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STM8AF61xx, STM8AF51xx Low speed internal RC oscillator (LSI 5.0 V and T DD Table 26. LSI oscillator characteristics Symbol f Frequency LSI t LSI oscillator wake-up time su(LSI) I LSI oscillator power consumption DD(LSI) 1. Data based on ...
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Electrical characteristics Table 28. Flash program memory/data EEPROM memory (continued) Symbol Erase/write cycles (program memory Erase/write cycles (data memory) Supply current (Flash programming erasing for 1 to 128 bytes (block) I Supply current (standby mode) ...
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STM8AF61xx, STM8AF51xx Software recommendations The software flowchart must include the management of runaway conditions such as: ● Corrupted program counter ● Unexpected reset ● Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program ...
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... Static latch-up class DLU Dynamic latch-up class 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). ...
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STM8AF61xx, STM8AF51xx 11.3.5 I/O port pin characteristics General characteristics Subject to general operating conditions for V be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull- down resistor. Table ...
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Electrical characteristics Figure 12. Recommended NRST pin protection External reset circuit 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the V Otherwise the ...
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STM8AF61xx, STM8AF51xx Figure 15. Typical V Figure 16. Typical V 11.3.6 TIM timer characteristics Subject to general operating conditions for V Table 34. TIM characteristics Symbol t Input capture pulse time w(ICAP)in t Timer resolution time res(TIM) ...
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Electrical characteristics 11.3.7 Communications interfaces SPI serial peripheral interface (master mode) General operating conditions: C Table 35. SSP master mode characteristics Symbol f SPI clock frequency SCK t SPI clock rise time r(SCK) t SPI clock fall time f(SCK) t ...
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STM8AF61xx, STM8AF51xx Figure 17. SPI configuration - master mode, single transfer NSS OUTPUT CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 CPHA = 1 CPO L= 0 CPHA = 1 CPOL = 1 MISO INPUT Don’t ...
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Electrical characteristics SPI serial peripheral interface (slave mode) Subject to general operating conditions with C Table 36. SPI slave mode characteristics Symbol f SPI clock frequency SCK NSS input setup time w.r.t SCK first t su(NSS) edge NSS input hold ...
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STM8AF61xx, STM8AF51xx Figure 21. SPI configuration - slave mode with CPHA = 0, continous transfer 1.5*t NSS INPUT CPOL=0 CPOL=1 MISO OUTPUT MOSI Don’t care INPUT Figure 22. SPI configuration, slave mode with CPHA = 1, single transfer NSS INPUT ...
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Electrical characteristics 2 Table 37 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t r(SDA) SDA and SCL rise time t ...
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STM8AF61xx, STM8AF51xx 11.3.8 10-bit ADC characteristics Subject to general operating conditions for V specified. Table 38. ADC characteristics Symbol f ADC clock frequency ADC V Conversion voltage range AIN Internal sample and hold C ADC capacitor (1) Minimum sampling time ...
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Electrical characteristics Table 40. ADC accuracy with f Symbol |E | Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error L 1. ADC accuracy ...
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STM8AF61xx, STM8AF51xx 11.4 Thermal characteristics The maximum chip junction temperature (T Table 17: General operating conditions on page The maximum chip-junction temperature, T using the following equation: Where: is the maximum ambient temperature in ° C – T Amax Θ ...
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Electrical characteristics 11.4.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order codes (see Figure 30: STM8A order codes on page The following example shows how to calculate the temperature range needed ...
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STM8AF61xx, STM8AF51xx 12 Package characteristics In order to meet environmental requirements, ST offers these devices in ECOPACK packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the ...
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Package characteristics 12.1 Package mechanical data Figure 26. 80-pin low profile quad flat package (14 x 14) Table 42. 80-pin low profile quad flat package mechanical data Dim ...
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STM8AF61xx, STM8AF51xx Figure 27. 64-pin low profile quad flat package (10 x 10) Pin 1 identification Table 43. 64-pin low profile quad flat package mechanical data Dim ...
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Package characteristics Figure 28. 48-pin low profile quad flat package ( Table 44. 48-pin low profile quad flat package mechanical data Dim Values in ...
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STM8AF61xx, STM8AF51xx Figure 29. 32-pin low profile quad flat package ( Available only for STM8A products with Kbytes Flash Table 45. 32-pin low profile quad flat package mechanical data Dim ...
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Ordering information 13 Ordering information Figure 30. STM8A order codes STM8A Product family STM8A....8-bit microcontroller Program memory type R....Mask ROM (no character) F....Flash + EEPROM P....FASTROM no EEPROM H....Flash no EEPROM Q....FASTROM + EEPROM Device family 5x - CAN/LIN 6x ...
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... In addition, STM8 application development is supported by a low-cost in- circuit debugger/programmer. The STice is the fourth generation of full-featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including tracing, profiling and code coverage analysis to help detect execution bottlenecks and dead code. ...
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STM8 development tools 14.2 Software tools STM8 development tools are supported by a complete, free software package from STMi- croelectronics that includes ST7/STM8 visual develop (STVD7) IDE and the ST7/STM8 visual programmer (STVP) software interface. STVD provides seamless integration of ...
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STM8AF61xx, STM8AF51xx 15 Revision history Table 46. Document revision history Date 31-Jan-2008 Revision Rev 1 Initial release Revision history Changes 83/84 ...
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... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...