stm8af6199 STMicroelectronics, stm8af6199 Datasheet
stm8af6199
Related parts for stm8af6199
stm8af6199 Summary of contents
Page 1
Automotive 8-bit MCU, with up to 128 Kbytes Flash, EEPROM, 10-bit ADC, timers, LIN, CAN, USART, SPI, I Features Core ■ Max MHz CPU ■ Advanced STM8A core with Harvard architecture and 3-stage pipeline ■ Average 1.6 ...
Page 2
Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
STM8AF61xx, STM8AF51xx 5.7.4 5.8 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
Contents 11.3.6 11.3.7 11.3.8 11.3.9 11.3.10 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
STM8AF61xx, STM8AF51xx List of tables Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
List of tables Table 47. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 7
STM8AF61xx, STM8AF51xx List of figures Figure 1. STM8A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
Introduction 1 Introduction This datasheet refers to the STM8AF61xx, STM8AH61xx, STM8AF51xx, STM8AH51xx products with 48 to 128 Kbytes of program memory. The STM8AF51xx and STM8AH51xx are hereafter referred to as the STM8AF/H51xx and the STM8AF61xx and STM8AH61xx are hereafter referred ...
Page 9
STM8AF61xx, STM8AF51xx 2 Description The STM8A automotive 8-bit microcontrollers offer from 48 to 128 Kbytes of program memory and integrated true data EEPROM. The STM8AF/H51xx series feature a CAN interface. All devices of the STM8A product line provide the following ...
Page 10
Product line-up 3 Product line-up . Table 2. STM8AF/H51xx product line-up with CAN Order code Package (bytes) STM8AF/H51AAT LQFP80 (14x14) STM8AF/H519AT STM8AF/H51A9T STM8AF/H5199T LQFP64 STM8AF/H5189T (10x10) STM8AF/H5179T STM8AF/H5169T STM8AF/H51A8T STM8AF/H5198T LQFP48 (1) (7x7) STM8AF/H5188T STM8AF/H5178T 1. QFN package planned ² ...
Page 11
STM8AF61xx, STM8AF51xx 4 Block diagram Figure 1. STM8A block diagram Reset Single wire debug interf. Master/slave autosynchro 400 Kbit/s 10 Mbit/s LIN master SPI emul. 1 Mbit/s 16 channels Reset block Clock controller Reset Detector POR PDR Clock to peripherals ...
Page 12
Product overview 5 Product overview The following section intends to give an overview of the basic features of the STM8A functional modules and peripherals. For more detailed information please refer to the STM8A microcontroller family reference manual (RM0009). 5.1 Central ...
Page 13
STM8AF61xx, STM8AF51xx 5.2 Single wire interface module (SWIM) and debug module The single wire interface module, SWIM, together with an integrated debug module, permits non-intrusive, real-time in-circuit debugging and fast memory programming. 5.2.1 SWIM Single wire interface for direct access ...
Page 14
Product overview 5.4.2 Write protection (WP) Write protection in application mode is intended to avoid unintentional overwriting of the memory in case of user software malfunction. Code update in user mode is still possible after execution of a specific MASS ...
Page 15
STM8AF61xx, STM8AF51xx 5.4.3 Read-out protection (ROP) STM8A devices provide a read-out protection of the code and data memory by programming the lock byte at address 4800h with the value AAh. Read-out protection prevents reading and writing the program and data ...
Page 16
Product overview 5.5 Low-power operating modes The product features various low-power modes: ● Slow mode: Prescaled CPU clock, selected peripherals at full clock speed ● Active halt mode: CPU and peripheral clocks are stopped ● Halt mode: CPU and peripheral ...
Page 17
STM8AF61xx, STM8AF51xx 5.6.2 Internal 16 MHz RC oscillator ● Default clock after reset 2 MHz (16 MHz/8) ● Wake-up time: < 2 µs User trimming The register CLK_HSITRIMR frequency tuning to a precision the application program. The ...
Page 18
Product overview 5.7 Timers 5.7.1 Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications. The WDG timer activity is controlled by the application program or option bytes. Once the watchdog is activated, ...
Page 19
STM8AF61xx, STM8AF51xx 5.7.3 Multipurpose and PWM timers STM8A devices described in this datasheet, contain up to three 16-bit multipurpose and PWM timers providing nine CAPCOM channels in total. Table 4. STM8A timer configuration Timer Counter Timer1 Timer2 16 Timer3 Timer4 ...
Page 20
Product overview 5.8 ADC The STM8A products described in this datasheet, contain a 10-bit successive approximation ADC with 16 multiplexed input channels. General features: ● 10-bit ADC with channels ● Input voltage range ● ...
Page 21
STM8AF61xx, STM8AF51xx Full duplex, asynchronous communication ● NRZ standard format (mark/space) ● High-precision baud rate generator system – Common programmable transmit and receive baud rates up to 2.5 M baud ● Programmable data word length ( bits) ● ...
Page 22
Product overview 5.9.2 LINUART Main features ● LIN master/slave rev. 2.1 compliant ● Auto-synchronization in LIN slave mode ● 16-bit baud rate prescaler ● 1 Mbit full duplex SCI LIN master ● Autonomous header handling ● 13-bit LIN synch break ...
Page 23
STM8AF61xx, STM8AF51xx 2 5.9 ● master features: – Clock generation – Start and stop generation ● slave features: – Programmable I – Stop bit detection ● Generation and detection of 7-bit/10-bit addressing ...
Page 24
Product overview ● Filtering modes: – Mask mode permitting ID range filtering – ID list mode ● Time triggered communication option – Disable automatic retransmission mode – 16-bit free running timer – Configurable timer resolution – Time stamp sent in ...
Page 25
STM8AF61xx, STM8AF51xx 6 Pinouts and pin description 6.1 Package pinouts Figure 3. LQFP 80-pin pinout NRST OSCIN/PA1 OSCOUT/PA2 V SSIO_1 V SS VCAP DDIO_1 TIM2_CC3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 (HS) PH0 HS) PH1 ( PH2 PH3 AIN15/PF7 AIN14/PF6 ...
Page 26
Pinouts and pin description Figure 4. LQFP 64-pin pinout OSCIN/PA1 OSCOUT/PA2 TIM2_CC3/PA3 USART_RX/PA4 USART_TX/PA5 USART_CK/PA6 1. The CAN interface is only available on the STM8AF/H51xx product line 26/100 ...
Page 27
STM8AF61xx, STM8AF51xx Figure 5. LQFP 48-pin pinout 1. The CAN interface is only available on the STM8AF/H51xx product line NRST 1 OSCIN/PA1 2 OSCOUT/PA2 SSIO_1 ...
Page 28
Pinouts and pin description Figure 6. LQFP 32-pin pinout 6.2 Pin description Table 5. Legend/abbreviation for Type Level Output speed Port and control configuration Reset state is shown in bold. 28/100 NRST ...
Page 29
STM8AF61xx, STM8AF51xx Table 6. STM8A microcontroller family pin description Pin number Pin name NRST PA1/OSCIN PA2/OSCOUT SSIO_1 ...
Page 30
Pinouts and pin description Table 6. STM8A microcontroller family pin description (continued) Pin number Pin name PB7/AIN7 PB6/AIN6 PB5/AIN5 PB4/AIN4 ...
Page 31
STM8AF61xx, STM8AF51xx Table 6. STM8A microcontroller family pin description (continued) Pin number Pin name PC4/TIM1_CC4 PC5/SPI_SCK SSIO_2 DDIO_2 ...
Page 32
Pinouts and pin description Table 6. STM8A microcontroller family pin description (continued) Pin number Pin name PD0/TIM3_CC2 PD1/SWIM PD2/TIM3_CC1 PD3/TIM2_CC2 PD4/TIM2_CC1 ...
Page 33
STM8AF61xx, STM8AF51xx 7 Memory map Figure 7. Register and memory map Table 7. Stack and RAM partitioning Product Kbytes 128 00 0000 Kbytes RAM Kbyte stack 00 1800 Reserved 00 4000 ...
Page 34
Interrupt table 8 Interrupt table Table 8. STM8A interrupt table Source Priority block - Reset - TRAP 0 TLI 1 AWU Clock 2 controller 3 MISC 4 MISC 5 MISC 6 MISC 7 MISC 8 CAN 9 CAN 10 SPI ...
Page 35
STM8AF61xx, STM8AF51xx Table 8. STM8A interrupt table (continued) Source Priority block 22 ADC 23 Timer 4 24 Reserved 1. Also unused interrupts should be initialized with “IRET” for robust programming. Interrupt vector Description address End of conversion 8060h Update/overflow 8064h ...
Page 36
Register mapping 9 Register mapping Table 9. STM8A I/O port hardware register map Address Block 00 5000h 00 5001h 00 5002h Port A 00 5003h 00 5004h 00 5005h 00 5006h 00 5007h Port B 00 5008h 00 5009h 00 ...
Page 37
STM8AF61xx, STM8AF51xx Table 9. STM8A I/O port hardware register map (continued) Address Block 00 501Eh 00 501Fh 00 5020h Port G 00 5021h 00 5022h 00 5023h 00 5024h 00 5025h Port H 00 5026h 00 5027h 00 5028h 00 ...
Page 38
Register mapping Table 10. STM8A general hardware register map Address Block 00 5050h to 00 5059h 00 505Ah 00 505Bh 00 505Ch Flash 00 505Dh 00 505Eh 00 505Fh 00 5060h to 00 5061h 00 5062h Flash 00 5063h 00 ...
Page 39
STM8AF61xx, STM8AF51xx Table 10. STM8A general hardware register map (continued) Address Block 00 50C3h 00 50C4h 00 50C5h 00 50C6h 00 50C7h CLK 00 50C8h 00 50C9h 00 50CAh 00 50CBh 00 50CCh 00 50CDh 00 50CEh to 00 50D0h ...
Page 40
Register mapping Table 10. STM8A general hardware register map (continued) Address Block 00 5200h 00 5201h 00 5202h 00 5203h SPI 00 5204h 00 5205h 00 5206h 00 5207h 00 5208h to 00 520Fh 00 5210h 00 5211h 00 5212h ...
Page 41
STM8AF61xx, STM8AF51xx Table 10. STM8A general hardware register map (continued) Address Block 00 5230h 00 5231h 00 5232h 00 5233h 00 5234h 00 5235h USART 00 5236h 00 5237h 00 5238h 00 5239h 00 523Ah 00 523Bh to 00 523Fh ...
Page 42
Register mapping Table 10. STM8A general hardware register map (continued) Address Block 00 5250h 00 5251h 00 5252h 00 5253h 00 5254h 00 5255h 00 5256h 00 5257h 00 5258h 00 5259h 00 525Ah 00 525Bh 00 525Ch 00 525Dh ...
Page 43
STM8AF61xx, STM8AF51xx Table 10. STM8A general hardware register map (continued) Address Block 00 5300h 00 5301h 00 5302h 00 5303h 00 5304h 00 5305h 00 5306h 00 5307h 00 5308h 00 5309h 00 530Ah TIM2 00 530Bh 00 530Ch 00 ...
Page 44
Register mapping Table 10. STM8A general hardware register map (continued) Address Block 00 5320h 00 5321h 00 5322h 00 5323h 00 5324h 00 5325h 00 5326h 00 5327h 00 5328h TIM3 00 5329h 00 532Ah 00 532Bh 00 532Ch 00 ...
Page 45
STM8AF61xx, STM8AF51xx Table 10. STM8A general hardware register map (continued) Address Block 00 5400h 00 5401h 00 5402h 00 5403h ADC 00 5404h 00 5405h 00 5406h 00 5407h 00 5408h to 00 541Fh 00 5420h 00 5421h 00 5422h ...
Page 46
Register mapping Table 10. STM8A general hardware register map (continued) Address Block 00 5438h to 00 57FFh 5800h 5801h 5802h 5803h 5804h TMU 5805h 5806h 5807h 5808h 46/100 Register label Register name Reserved area (968 bytes) TU_KEYS_REG0 TMU key register ...
Page 47
STM8AF61xx, STM8AF51xx Table 11. CPU/SWIM/debug module/interrupt controller registers Address Block 00 7F00h 00 7F01h 00 7F02h 00 7F03h 00 7F04h 00 7F05h CPU 00 7F06h 00 7F07h 00 7F08h 00 7F09h 00 7F0Ah 00 7F0Bh to 00 7F5Fh 00 7F60h ...
Page 48
Register mapping Table 11. CPU/SWIM/debug module/interrupt controller registers (continued) Address Block 00 7F90h 00 7F91h 00 7F92h 00 7F93h 00 7F94h 00 7F95h 00 7F96h 00 7F97h 00 7F98h 00 7F99h 00 7F9Ah 00 7F9Bh to 00 7F9Fh 48/100 Register ...
Page 49
STM8AF61xx, STM8AF51xx 10 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated block of the memory. Each option byte has to be stored twice, ...
Page 50
Option bytes Table 12. Option bytes (continued) Option Option Addr. name byte no. 4810h OPT8 4811h OPT9 4812h OPT10 4813h OPT11 4814h TMU OPT12 4815h OPT13 4816h OPT14 4817h OPT15 4818h OPT16 4819h to 487D 487E OPT17 Boot- loader 487F ...
Page 51
STM8AF61xx, STM8AF51xx Table 13. Option byte description Option byte no. OPT0 OPT1 OPT2 Description ROP[7:0]: Memory readout protection (ROP) AAh: Enable readout protection (write access via SWIM protocol) Note: Refer to the STM8A microcontroller family reference manual (RM0009) section on ...
Page 52
Option bytes Table 13. Option byte description (continued) Option byte no. OPT3 OPT4 OPT5 OPT6 OPT7 OPT8 OPT9 OPT10 OPT11 52/100 Description LSI_EN: Low speed internal clock enable 0: LSI clock is not available as CPU clock source 1: LSI ...
Page 53
STM8AF61xx, STM8AF51xx Table 13. Option byte description (continued) Option byte no. OPT12 OPT13 OPT14 OPT15 OPT16 OPT17 Description TMU_KEY 5 [7:0]: Temporary unprotection key 4 Temporary unprotection key: Must be different from 00h or FFh TMU_KEY 6 [7:0]: Temporary unprotection ...
Page 54
Electrical characteristics 11 Electrical characteristics 11.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 11.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
Page 55
STM8AF61xx, STM8AF51xx 11.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 9. Pin input voltage 11.2 Absolute maximum ratings Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage ...
Page 56
Electrical characteristics Table 15. Current characteristics Symbol I Total current into V VDD I Total current out of V VSS Output current sunk by any I/O and control pin I IO Output current source by any I/Os and control pin ...
Page 57
STM8AF61xx, STM8AF51xx 11.3 Operating conditions Table 17. General operating conditions Symbol f Internal CPU clock frequency CPU V V Standard operating voltage DD/ DD_IO Junction temperature range J Figure 10. f CPUmax Functionality not guaranteed in this ...
Page 58
Electrical characteristics Table 18. Operating conditions at power-up/power-down Symbol Parameter V rise time rate DD t VDD V fall time rate DD Reset release delay t TEMP Reset generation (3) delay Power-on reset V IT+ threshold Brown-out reset V IT- ...
Page 59
STM8AF61xx, STM8AF51xx Table 19. Total current consumption in run, wait and slow mode at V Symbol Parameter Supply I current in DD(RUN) run mode Supply I current in DD(RUN) run mode Supply I current in DD(RUN) run mode Conditions HSE ...
Page 60
Electrical characteristics Table 19. Total current consumption in run, wait and slow mode at V Symbol Parameter Supply I current in DD(RUN) run mode Supply I current in DD(WFI) wait mode Supply I current in DD(SLOW) slow mode 1. Prodution ...
Page 61
STM8AF61xx, STM8AF51xx Table 20. Total current consumption and timing in halt, fast active halt and slow active halt modes at V Symbol I Supply current in halt mode DD(H) Supply current in fast active halt I DD(FAH) mode Supply current ...
Page 62
Electrical characteristics Table 21. Total current consumption in run, wait and slow mode at V Symbol Parameter Supply I current in DD(RUN) run mode Supply I current in DD(RUN) run mode Supply I current in DD(RUN) run mode 62/100 Conditions ...
Page 63
STM8AF61xx, STM8AF51xx Table 21. Total current consumption in run, wait and slow mode at V Symbol Parameter Supply I current in DD(WFI) wait mode Supply I current in DD(SLOW) slow mode Conditions HSE Crystal oscillator CPU MASTER ...
Page 64
Electrical characteristics Table 22. Total current consumption and timing in halt, fast active halt and slow active halt modes at V Symbol I Supply current in halt mode DD(H) Supply current in fast active halt I DD(FAH) mode Supply current ...
Page 65
STM8AF61xx, STM8AF51xx On-chip peripherals Table 23. Typical peripheral current consumption V Symbol I TIM1 supply current DD(TIM1) I TIM2 supply current DD(TIM2) I TIM3 supply current DD(TIM3) I TIM4 supply current DD(TIM4) I USART supply current DD(USART) I LINUART supply ...
Page 66
Electrical characteristics Current consumption curves Figure 11 to Figure 16 show typical current consumption measured with code executing in RAM. Figure 11. Typ. I DD(RUN)HSE @ MHz, periph = on CPU ...
Page 67
STM8AF61xx, STM8AF51xx 11.3.2 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for V Table 24. HSE user external clock characteristics Symbol User external clock source f HSE_ext frequency V Comparator hysteresis HSEdHL OSCIN ...
Page 68
Electrical characteristics Table 25. HSE oscillator characteristics Symbol Parameter R Feedback resistor F (1) C Recommended load capacitance I HSE oscillator power consumption DD(HSE) g Oscillator transconductance m (3) t Startup time SU(HSE approximately equivalent to 2 ...
Page 69
STM8AF61xx, STM8AF51xx 11.3.3 Internal clock sources and timing characteristics Subject to general operating conditions for V High speed internal RC oscillator (HSI) Table 26. HSI oscillator characteristics Symbol Parameter f Frequency HSI HSI oscillator user trimming accuracy ACC HS HSI ...
Page 70
Electrical characteristics Low speed internal RC oscillator (LSI) Subject to general operating conditions for V Table 27. LSI oscillator characteristics Symbol f Frequency LSI t LSI oscillator wake-up time su(LSI) 1. Data based on characterization results, not tested in production. ...
Page 71
STM8AF61xx, STM8AF51xx 11.3.4 Memory characteristics RAM and hardware registers Table 28. RAM and hardware registers Symbol V Data retention mode RM 1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset hardware ...
Page 72
Electrical characteristics 11.3.5 I/O port pin characteristics General characteristics Subject to general operating conditions for V unused pins must be kept at a fixed voltage, using the output mode of the I/O for example or an external pull-up or pull-down ...
Page 73
STM8AF61xx, STM8AF51xx Figure 21. Typical Figure 22. Typical pull-up resistance Figure 23. Typical pull-up current I Note: The pull- pure resistor (slope ...
Page 74
Electrical characteristics Typical output level curves Figure 24 to Figure 33 show typical output level curves measured with output on a single pin. Figure 24. Typ ports) -40°C 1.5 25°C 85°C 1.25 125°C 1 0.75 ...
Page 75
STM8AF61xx, STM8AF51xx Figure 30. Typ (standard ports) -40°C 2 25°C 1.75 85°C 125°C 1.5 1.25 1 0.75 0.5 0. [mA] OH Figure 32. Typ ...
Page 76
Electrical characteristics 11.3.6 Reset pin characteristics Subject to general operating conditions for V Table 31. NRST pin characteristics Symbol V NRST input low level voltage IL(NRST) V NRST input high level voltage IH(NRST) V NRST output low level voltage OL(NRST) ...
Page 77
STM8AF61xx, STM8AF51xx Figure 35. Typical NRST pull-up resistance Figure 36. Typical NRST pull-up current I 140 120 100 The reset network shown in must ensure that the level on the NRST pin ...
Page 78
Electrical characteristics 11.3.7 TIM and 4 timer characteristics Subject to general operating conditions for V Table 32. TIM characteristics Symbol t Input capture pulse time w(ICAP)in t Timer resolution time res(TIM) f Timer external ...
Page 79
STM8AF61xx, STM8AF51xx SPI serial peripheral interface 11.3.8 Unless otherwise specified, the parameters given in performed under ambient temperature, f conditions. t MASTER Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). ...
Page 80
Electrical characteristics Figure 38. SPI timing diagram where slave mode and CPHA = 0 NSS input t SU(NSS) CPHA= 0 CPOL=0 t w(SCKH) CPHA w(SCKL) CPOL=1 t a(SO) MISO OUT su(SI) MOSI I NPUT Figure ...
Page 81
STM8AF61xx, STM8AF51xx Figure 40. SPI timing diagram - master mode High NSS input CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 t su(MI) MISO INP UT MOSI OUTUT 1. Measurement points are at CMOS levels: 0 ...
Page 82
Electrical characteristics 2 11.3 interface characteristics 2 Table 34 characteristics Symbol t SCL clock low time w(SCLL) t SCL clock high time w(SCLH) t SDA setup time su(SDA) t SDA data hold time h(SDA) t SDA ...
Page 83
STM8AF61xx, STM8AF51xx 11.3.10 10-bit ADC characteristics Subject to general operating conditions for V specified. Table 35. ADC characteristics Symbol f ADC clock frequency ADC V Analog supply DDA V Positive reference voltage REF+ V Negative reference voltage REF- V Conversion ...
Page 84
Electrical characteristics Table 36. ADC accuracy with R Symbol |E | Total unadjusted error Offset error Gain error Differential linearity error Integral linearity error L 1. TBD = ...
Page 85
STM8AF61xx, STM8AF51xx Figure 42. Typical application with ADC V AIN 11.3.11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) While executing a simple application (toggling 2 LEDs through I/O ports), the ...
Page 86
Electrical characteristics Table 38. EMS data Symbol Voltage limits to be applied on any I/O pin to V FESD induce a functional disturbance Fast transient voltage burst limits applied through 100 EFTB pins to ...
Page 87
... Symbol Static latch-up class LU 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B class strictly covers all the JEDEC criteria (international standard). ...
Page 88
Electrical characteristics 11.4 Thermal characteristics The maximum chip junction temperature (T Table 17: General operating conditions on page 57 The maximum chip-junction temperature, T using the following equation: Where: is the maximum ambient temperature in ° C – T Amax ...
Page 89
STM8AF61xx, STM8AF51xx 11.4.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the order code (see Figure 47: STM8A order codes on page 95 The following example shows how to calculate the temperature range ...
Page 90
Package characteristics 12 Package characteristics To meet environmental requirements, ST offers these devices in ECOPACK These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, ...
Page 91
STM8AF61xx, STM8AF51xx 12.1 Package mechanical data Figure 43. 80-pin low profile quad flat package ( Pin 1 identification 1 Table 43. 80-pin low profile quad flat package mechanical data Dim ...
Page 92
Package characteristics Figure 44. 64-pin low profile quad flat package (10 x 10) Pin 1 identification 1. Available only for STM8A products with Kbytes Flash Table 44. 64-pin low profile quad flat package mechanical data Dim. A ...
Page 93
STM8AF61xx, STM8AF51xx Figure 45. 48-pin low profile quad flat package ( Table 45. 48-pin low profile quad flat package mechanical data Dim θ Values in ...
Page 94
Package characteristics Figure 46. 32-pin low profile quad flat package ( Table 46. 32-pin low profile quad flat package mechanical data Dim θ Values in ...
Page 95
STM8AF61xx, STM8AF51xx 13 Ordering information Figure 47. STM8A order codes STM8A Product family STM8A....8-bit microcontroller Program memory type F....Flash + EEPROM P....FASTROM no EEPROM H....Flash no EEPROM Q....FASTROM + EEPROM Device family 5x - CAN/LIN 6x - LIN only 1. ...
Page 96
... In addition, STM8A application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full-featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including tracing, profiling and code coverage analysis to help detect execution bottlenecks and dead code. ...
Page 97
... Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST visual develop (STVD) IDE and the ST visual program- mer (STVP) software interface. STVD provides seamless integration of the Cosmic C com- piler for STM8, which is available in a free version that outputs Kbytes of code. ...
Page 98
Revision history 15 Revision history Table 47. Document revision history Date 31-Jan-2008 22-Aug-2008 98/100 Revision Rev 1 Initial release Added ‘H’ products to the datasheet (Flash no EEPROM). Features on page 1: Updated Memories, management, Communication interfaces pins by 1. ...
Page 99
STM8AF61xx, STM8AF51xx Table 47. Document revision history (continued) Date 22-Aug-2008 16-Sep-2008 Revision Table 26: Removed ACC parameters; amended data and footnotes. Table 28: Amended data. Table 29: Updated names and data of N Table 30: Added V OH parameter. Removed: ...
Page 100
... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...