tmp86c408idmg TOSHIBA Semiconductor CORPORATION, tmp86c408idmg Datasheet - Page 73
tmp86c408idmg
Manufacturer Part Number
tmp86c408idmg
Description
Cmos 8-bit Microcontroller
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP86C408IDMG.pdf
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7.3.4 Address Trap Reset
attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”) or the SFR
area, address trap reset will be generated.
24/fc [s] (1.5 µs @ fc = 16.0 MHz).
While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an
When an address trap reset request is generated, the internal hardware is reset. The reset time is maximum
Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-fre-
quency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccura-
cies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate
value because it has slight errors.
Page 63
TMP86C408IDMG
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