tmp89fm42 TOSHIBA Semiconductor CORPORATION, tmp89fm42 Datasheet - Page 292

• Manufacturer Part Number: tmp89fm42
• Description: 8 Bit Microcontroller
• Manufacturer: TOSHIBA Semiconductor CORPORATION

18.5 Data Transfer of I2C Bus
18. Serial Bus Interface (SBI)
RA001
Example :Initialize a device
18.5 Data Transfer of I
18.5.1 Device initialization
18.5.2 Start condition and slave address generation
serial bus interface mode.
of clocks for an acknowledge signal, to enable the slave address match detection and the GENERAL CALL
detection, and set the data length to 8 bits. Set T
SBI0CR2<SWRST> to "00" for specifying the default setting to a slave receiver mode.
SBI0DBR.
tion is generated on a bus and then, the slave address and the direction bit which are set to the SBI0DBR are
output. The time from generating the START condition until the falling SBI0 pin takes t
"0". The SCL0 pin is pulled down to the low level while SBI0CR2<PIN> is "0". When an interrupt request
occurs, SBI0CR2<TRX> changes by the hardware according to the direction bit only when an acknowledge
signal is returned from the slave device.
Set POFFCR1<SBI0EN> to "1".
After confirming that the serial bus interface pin is high level, set SBI0CR2<SBIM> to "1" to select the
Set SBI0CR1<ACK> to "1", SBI0CR1<NOACK> to "0" and SBI0CR1<BC> to "000" to count the number
Set a slave address at I2C0AR<SA> and set I2C0AR<ALS> to "0" to select the I
Finally, set SBI0CR2<MST>, SBI0CR2<TRX> and SBI0CR2<BB> to "0", SBI0CR2<PIN> to "1" and
Note:The initialization of a serial bus interface circuit must be complete within the time from all devices which are
Confirm a bus free status (SBI0SR2<BB>="0").
Set SBI0CR1<ACK> to "1" and specify a slave address and a direction bit to be transmitted to the
By writing "1" to SBI0CR2<MST>, SBI0CR2<TRX>, SBI0CR2<BB> and SBI0CR2<PIN>, the start condi-
An interrupt request occurs at the 9th falling edge of a SCL clock cycle, and SBI0CR2<PIN> is cleared to
Note 1: Do not write a slave address to the SBI0DBR while data is transferred. If data is written to the SBI0DBR,
Note 2: The bus free state must be confirmed by software within 98.0 Ps (the shortest transmitting time according to
CHK_PORT:
connected to a bus have initialized to and device does not generate a start condition. If not, the data can not
be received correctly because the other device starts transferring before an end of the initialization of a serial
bus interface circuit.
data to be output may be destroyed.
the standard mode I
I
set "1" to SBI0CR2<MST>, SBI0CR2<TRX>, SBI0CR2<BB> and SBI0CR2<PIN> to generate the start
conditions. If the writing of slave address and setting of SBI0CR2<MST>, SBI0CR2<TRX>, SBI0CR2<BB>
and SBI0CR2<PIN> doesn't finish within 98.0Ps or 23.7Ps, the other masters may start the transferring and
the slave address data written in SBI0DBR may be broken.
2
C bus standard) after setting of the slave address to be output. Only when the bus free state is confirmed,
CMP
JR
LD
LD
LD
LD
2
C Bus
2
(P2PRD), 0x0C
NZ, CHK_PORT
(SBI0CR2), 0x18
(SBI0CR1), 0x16
(I2C0AR), 0xa0
(SBI0CR2), 0x18
C bus standard) or 23.7Ps (the shortest transmitting time according to the fast mode
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HIGH
and T
; Checks whether the serial bus interface pin is at the high level
; Selects the serial bus interface mode
; Selects the acknowledgment mode and sets SBI0CR1<SCK> to
"110"
; Sets the slave address to 1010000 and selects the I2C bus mode
; Selects the slave receiver mode
LOW
at SBI0CR1<SCK>.
2
C bus mode.
HIGH
.
TMP89FM42