tmp89fh40 TOSHIBA Semiconductor CORPORATION, tmp89fh40 Datasheet - Page 267
tmp89fh40
Manufacturer Part Number
tmp89fh40
Description
8 Bit Microcontroller Tlcs-870/c1 Series
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP89FH40.pdf
(426 pages)
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RA001
17.4
Table 17-3 Transfer Baud Rate
<SIOCKS>
17.4.1
17.4.2
17.4.3
SIO0CR
000
001
010
011
100
101
110
Functions
DIR> to "0" selects LSB first as the transfer format. In this case, the serial data is transferred in sequence from
the least significant bit.
transferred in sequence from the most significant bit.
serial clock is output from the SCLK0 pin. The serial data is transferred in synchronization with the edge of the
SCLK0 pin output.
clock must be input to the SCLK0 pin. The serial data is transferred in synchronization with the edge of the
external clock.
"17.4.3 Transfer edge selection".
and the data is received in synchronization with the rising edge of the clock.
and the data is received in synchronization with the falling edge of the clock.
The transfer format can be set to either MSB or LSB first by using SIO0CR<SIODIR>. Setting SIO0CR<SIO-
Setting SIO0CR<SIODIR> to "1" selects MSB first as the transfer format. In this case, the serial data is
The serial clock can be selected by using SIO0CR<SIOCKS>.
Setting SIO0CR<SIOCKS> to "000" to "110" selects the internal clock as the serial clock. In this case, the
Setting SIO0CR<SIOCKS> to "111" selects an external clock as the serial clock. In this case, an external serial
The serial data transfer edge can be selected for both the external and internal clocks. For details, refer to
NORMAL1/2 or
The serial data transfer edge can be selected by using SIOCR<SIOEDG>.
When SIOCR<SIOEDG> is "0", the data is transmitted in synchronization with the falling edge of the clock
When SIOCR<SIOEDG> is "1", the data is transmitted in synchronization with the rising edge of the clock
IDLE1/2 mode
Transfer format
Serial clock
Transfer edge selection
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
fcgck/2
Serial clock [Hz]
9
6
5
4
3
2
SLEEP1 mode
Table 17-4 Transfer Edge Selection
SLOW1/2 or
SIO0CR<SIOEDG>
fs/2
-
-
-
-
-
-
3
0
1
1-bit time
(μs)
128
0.5
16
8
4
2
1
fcgck=4MHz
Baud rate
7.813k
62.5k
(bps)
Data transmission
125k
250k
500k
1M
2M
Page 253
Falling edge
Rising edge
1-bit time
0.25
(μs)
0.5
64
8
4
2
1
fcgck=8MHz
Baud rate
15.625k
(bps)
125k
250k
500k
1M
2M
4M
Data reception
Falling edge
Rising edge
1-bit time
51.2
(μs)
6.4
3.2
1.6
0.8
0.4
0.2
fcgck=10MHz
Baud rate
19.531k
156.25k
312.5k
1.25M
(bps)
625k
2.5M
5M
1-bit time
TMP89FH40
(μs)
244
fs=32.768kHz
-
-
-
-
-
-
Baud rate
(bps)
4k
-
-
-
-
-
-
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