se97b NXP Semiconductors, se97b Datasheet

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se97b

Manufacturer Part Number
se97b
Description
Ddr Memory Module Temp Sensor With Integrated Spd
Manufacturer
NXP Semiconductors
Datasheet

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1. General description
Meets JEDEC Specification 42.4 TSE2002B1, 3 Jun 2009. The NXP Semiconductors
SE97B measures temperature from −40 °C to +125 °C with JEDEC Grade B ±1 °C
maximum accuracy between +75 °C and +95 °C critical zone and also provide 256 bytes
of EEPROM memory communicating via the I
DDR3 Dual In-Line Memory Module (DIMM) measuring the DRAM temperature in
accordance with the new JEDEC (JC-42.4) Mobile Platform Memory Module Temperature
Sensor Component specification and also replacing the Serial Presence Detect (SPD)
which is used to store memory module and vendor information.
The SE97B thermal sensor and EEPROM operates over the V
The TS consists of a ΔΣ Analog to Digital Converter (ADC) that monitors and updates its
own temperature readings 10 times per second, converts the reading to a digital data, and
latches them into the data temperature register. User-programmable registers, the
specification of upper/lower alarm and critical temperature trip points, EVENT output
control, and temperature shutdown, provide flexibility for DIMM temperature-sensing
applications.
When the temperature changes beyond the specified boundary limits, the SE97B outputs
an EVENT signal using an open-drain output that can be pulled up between 0.9 V and
3.6 V. The user has the option of setting the EVENT output signal polarity as either an
active LOW or active HIGH comparator output for thermostat operation, or as a
temperature event interrupt output for microprocessor-based systems. The EVENT output
can also be configured as only a critical temperature output.
The EEPROM is designed specifically for DRAM DIMMs SPD. The lower 128 bytes
(address 00h to 7Fh) can be Permanent Write Protected (PWP) or Reversible Write
Protected (RWP) by software. This allows DRAM vendor and product information to be
stored and write protected. The upper 128 bytes (address 80h to FFh) are not write
protected and can be used for general purpose data storage.
The SE97B has a single die for both the temp sensor and EEPROM for higher reliability
and supports the industry-standard 2-wire I
TIMEOUT function is supported to prevent system lock-ups. Manufacturer and Device ID
registers provide the ability to confirm the identity of the device. Three address pins allow
up to eight devices to be controlled on a single bus.
The SE98B is available as the SE97B thermal sensor only.
SE97B
DDR memory module temp sensor with integrated SPD
Rev. 01 — 27 January 2010
2
C-bus/SMBus serial interface. The SMBus
2
C-bus/SMBus. It is typically mounted on a
DD
range of 3.0 V to 3.6 V.
Product data sheet

Related parts for se97b

se97b Summary of contents

Page 1

... The upper 128 bytes (address 80h to FFh) are not write protected and can be used for general purpose data storage. The SE97B has a single die for both the temp sensor and EEPROM for higher reliability and supports the industry-standard 2-wire I TIMEOUT function is supported to prevent system lock-ups ...

Page 2

... NXP Semiconductors Table 1. Comparison of SE97 versus SE97B features Feature JEDEC specification Bit 8 ‘1’ Thermal Sensor shutdown Bit 8 ‘0’ Thermal Sensor active 2 I C-bus maximum frequency SCL and SDA V /V voltage levels IL IH Capabilities bit 6 SMBus Timeout EVENT pin operation ...

Page 3

... SE97B_1 Product data sheet DDR memory module temp sensor with integrated SPD Description plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 × 3 × 0.8 mm Rev. 01 — 27 January 2010 SE97B Version SOT1069-2 © NXP B.V. 2010. All rights reserved ...

Page 4

... LOCK PROTECTION • EVENT OUTPUT ON/OFF • EVENT OUTPUT POLARITY • EVENT OUTPUT STATUS • CLEAR EVENT OUTPUT STATUS POINTER REGISTER Fig 1. Block diagram of SE97B SE97B_1 Product data sheet DDR memory module temp sensor with integrated SPD POR BAND GAP TEMPERATURE SENSOR 11-BIT Δ ...

Page 5

... O Thermal alarm output for high/low and critical temperature limit (open-drain). Must have external pull-up resistor. 8 power device power supply (3 3.6 V) Rev. 01 — 27 January 2010 EVENT SE97BTP 6 SCL 5 SDA 002aae311 © NXP B.V. 2010. All rights reserved. SE97B ...

Page 6

... SMBus is from 10 kHz to 100 kHz. The host or bus master generates the SCL signal, and the SE97B uses the SCL signal to receive or send data on the SDA line. Data transfer is serial, bidirectional, and is one byte at a time with the Most Significant Bit (MSB) transferred first ...

Page 7

... EVENT pin. SE97B_1 Product data sheet DDR memory module temp sensor with integrated SPD Figure 4 shows an example of the measured Rev. 01 — 27 January 2010 SE97B © NXP B.V. 2010. All rights reserved ...

Page 8

... Temperature Register Status bits Critical Temp Bit 15 Bit 14 only mode Above Above Critical Alarm Trip Window SE97B − T hys − T trip(u) hys − trip(l) hys time (2) Bit 13 Below Alarm Window ...

Page 9

... EVENT is turned on. SE97B_1 Product data sheet DDR memory module temp sensor with integrated SPD temperature setting is programmed in the Critical Alarm Trip register (04h) as Rev. 01 — 27 January 2010 SE97B © NXP B.V. 2010. All rights reserved ...

Page 10

... BAW bit is set and the EVENT pin asserted (EventOutputControl = 1) and the part is switched to Interrupt mode, the EVENT is de-asserted. SE97B_1 Product data sheet DDR memory module temp sensor with integrated SPD Rev. 01 — 27 January 2010 SE97B only is th(crit) © NXP B.V. 2010. All rights reserved ...

Page 11

... The SE97B’s conversion rate is at least 125 ms. 7.4.1 What temperature is read when conversion is in progress The SE97B has been designed to ensure a valid temperature is always available ...

Page 12

... SMBus TIMEOUT The SE97B supports SMBus TIMEOUT feature. If the host holds SCL LOW more than 35 ms, the SE97B would reset its internal state machine to the bus IDLE state to prevent a system bus hang-up. This feature is turned on by default and release SDA. The SMBus TIMEOUT can be disabled by writing a ‘ ...

Page 13

... SMBus ALERT Fig 5. How SE97B responds to SMBus Alert Response Address 7.9 SMBus/I The data registers in this device are selected by the Pointer Register. At power-up, the Pointer Register is set to ‘00h’, the location for the Capability Register. The Pointer Register latches the last location to which it was set. Each data register falls into one of three types of user accessibility: • ...

Page 14

... read register address returned least significant byte data © NXP B.V. 2010. All rights reserved. SE97B 8 9 (cont.) (cont ACK by device ACK STOP by device by host 002aab412 8 9 (cont.) (cont.) ...

Page 15

... returned least significant byte data 2 C-bus or SMBus. … 07h 8 pages or 128 bytes 1 page or 16 bytes SE97B NACK STOP by host 002aac687 Figure 10 16 pages or 256 bytes 002aac812 © NXP B.V. 2010. All rights reserved ...

Page 16

... Fig 11. Byte Write timing 7.10.1.2 Page Write The SE97B contains 256 bytes of data, arranged in 16 pages of 16 bytes each. The page is selected by the four Most Significant Bits (MSB) of the address byte presented to the device after the slave address, while the four Least Significant Bits (LSB) point to the byte within the page ...

Page 17

... I(ov) [3] A0, A1, and A2 are compared against the respective external pins on the SE97B. Do not apply V Normal EEPROM read/write, Permanent Write Protection (PWP) and Read PWP. This special EEPROM command consists of a unique 4-bit fixed address (0110b) and the voltage level applied on the 3-bit hardware address. Normally, to address the memory array, the 4-bit fixed address is ‘ ...

Page 18

... (1) R/W acknowledge no acknowledge from slave from slave Rev. 01 — 27 January 2010 SE97B 2 C-bus. Each one is given a dummy data (1) (1) acknowledge from slave STOP condition 002aab356 ...

Page 19

... Read Permanent Write Protection (RPWP), Read Reversible Write Protection (RRWP), and Read Clear Reversible Write Protection (RCRWP) Read PWP, RWP, and CRWP allow the SE97B to be read in write protection mode. The instruction format is the same as that of the write protection except that the 8 set to 1 ...

Page 20

... Read operations 7.10.3.1 Current address read In Standby mode, the SE97B internal address counter points to the data byte immediately following the last byte accessed by a previous operation. If the ‘previous’ byte was the last byte in memory, then the address counter will point to the first memory byte, and so on. If the SE97B decodes a slave address with a ‘ ...

Page 21

... NXP Semiconductors 7.10.3.3 Sequential read If the master acknowledges the first data byte transmitted by the SE97B, then the device will continue transmitting as long as each data byte is acknowledged by the master (Figure will ‘wrap around’ to the beginning of memory, and so on. Sequential Read works with either ‘ ...

Page 22

... Register descriptions 8.1 Register overview This section describes all the registers used in the SE97B. The registers are used for latching the temperature reading, storing the low and high temperature limits, configuring, the hysteresis threshold of the ADC, as well as reporting status. The device uses the pointer register to access these registers ...

Page 23

... Alarm and Critical Trips interrupt capability Rev. 01 — 27 January 2010 11 10 RFU TRES WRNG supported within the range to(SMBus) SE97B HACC BCAP © NXP B.V. 2010. All rights reserved ...

Page 24

... When either of the Critical Trip or Alarm Window lock bits is set, these bits cannot be altered until unlocked. Rev. 01 — 27 January 2010 HEN R/W R EOCTL CVO R/W R/W R/W Figure 4 and © NXP B.V. 2010. All rights reserved. SE97B 8 SHMD 0 R/W 0 EMD 0 R/W Table 14 ...

Page 25

... When either of the Critical Trip or Alarm Window lock bits is set, this bit cannot be set until unlocked. However, it can be cleared at any time. When in shutdown mode, the SE97B will still respond to commands normally. When coming out of shutdown, the EVENT output remains de-asserted as a new temperature conversion is done ...

Page 26

... When the EP (EVENT Polarity) bit is changed, the EVENT output would immediately change state on the SE97B. A new Shutdown mode has been added on the SE97B with two states defined by the SMBus register EventSleepState = 0. Freeze state of EVENT output and EventSleepState = 1: de-asserted state of EVENT output. So now if the EP bit changes, the EVENT output state will change immediately even during shutdown ...

Page 27

... Rev. 01 — 27 January 2010 Above Critical Trip bit (bit 15) Temperature slope rising trip(u) − T falling trip(u) hys current temperature hysteresis set clear set clear clear SE97B Threshold temperature T th(crit) − th(crit) hys hysteresis hysteresis time 002aac799 © NXP B.V. 2010. All rights reserved ...

Page 28

... NXP B.V. 2010. All rights reserved. SE97B Hex E7D0h E190h E010h E004h E002h E000h FFFEh FFFCh FFF0h FF40h ...

Page 29

... Upper Boundary Alarm Trip Temperature (LSB = 0.25 °C) - RFU reserved; always ‘0’ Rev. 01 — 27 January 2010 128 °C 64 °C SIGN R/W R/W R °C 0.5 °C 0.25 ° R/W R/W R/W © NXP B.V. 2010. All rights reserved. SE97B °C 16 ° R/W R RFU RFU ...

Page 30

... R/W R/W R 128 °C 64 °C SIGN R/W R/W R °C 0.5 °C 0.25 ° R/W R/W R/W © NXP B.V. 2010. All rights reserved. SE97B °C 16 ° R/W R RFU RFU °C 16 ° R/W R RFU RFU ...

Page 31

... SIGN °C 0.5 °C 0.25 ° − T hys − T hys − T hys − T hys hys hys SE97B °C 16 ° 0.125 °C RFU © NXP B.V. 2010. All rights reserved ...

Page 32

... NXP Semiconductors 8.7 MANID — Manufacturer’s ID register (06h, 16-bit read-only) The SE97B Manufacturer’s ID register is intended to match NXP Semiconductors PCI SIG (1131h). Table 24. Bit Symbol Default Access Bit Symbol Default Access 8.8 DEVICEID — Device ID register (07h, 16-bit read-only) The SE97B device ID is A2h. The device revision is 03h. ...

Page 33

... When either Critical Trip or Alarm Window lock bits are set, this bit cannot be altered until unlocked. Rev. 01 — 27 January 2010 RFU Event IntrClear Flag RFU Sleep Mode Update State Mode R/W R/W R/W © NXP B.V. 2010. All rights reserved. SE97B Disable ARA R ...

Page 34

... SMBus TO is off TS is disabled and SPD low power SMBus TO is off read-only and SMBus TO is off Rev. 01 — 27 January 2010 SE97B …continued Power mode Use Full power, JEDEC - SMBus for oscillator is running TS and SPD (like SE97 on) ...

Page 35

... NXP Semiconductors 9. Application design-in information In a typical application, the SE97B behaves as a slave device and interfaces to a bus master (or host) via the SCL and SDA lines. The EVENT output is monitored by the host, and asserts when the temperature reading exceeds the programmed values in the alarm registers ...

Page 36

... EEPROM as the Serial Presence Detect (SPD). In the event of overheating, the SE97B triggers the EVENT output and the memory controller throttles the memory bus to slow the DRAM. The memory controller can also read the SE97B and watch the DRAM thermal behavior, taking preventive measures when necessary. ...

Page 37

... Hot plugging The SE97B can be used in hot plugging applications. Internal circuitry prevents damaging current backflow through the device when it is powered down, but with the I EVENT or address pins still connected. The open-drain SDA and EVENT pins (SCL and address pins are input only) effectively places the outputs in a high-impedance state during power-up and power-down, which prevents driver conflict and bus contention ...

Page 38

... SDA, SCL, A1, A2, EVENT pins −0.5 overvoltage input; A0 pin −1 SDA, EVENT pins - −65 Min Typ −1.0 < ±0.5 −2.0 < ±1.0 −3.0 < ±2 - 0.125 - 100 −30 - SE97B Max Unit +4.3 V +4.3 V +12.5 V +10 mA °C 150 °C +165 Max Unit °C +1.0 °C +2.0 °C +3.0 °C ...

Page 39

... DD −0.5 - [2] 7 0.05 × 0.10 × 1.2 1.8 −1.0 - −1.0 - −1.0 - −1 800 - DD to 0.1 μA typical at room temperature or DD(AV) SE97B Max Unit 3.6 V μA 320 μA 400 μ +0.3 × 0.2 V 0 μA +1.0 μA +1.0 μA +1.0 μA +1 μ ...

Page 40

... SCL 0.20 OL (V) 0. 0.08 3.0 V 0.04 0 − ( 0.2 3.0 V 0.1 0 − 3 SE97B 002aaf181 80 120 T (°C) amb 002aaf183 80 120 T (°C) amb 002aaf185 80 120 T (°C) amb © NXP B.V. 2010. All rights reserved ...

Page 41

... Rev. 01 — 27 January 2010 0.20 OL 0. 0.08 3.0 V 0.04 0 − 2 (conv/ − cy(W) (ms − SE97B 002aaf187 80 120 T (°C) amb 002aad886 80 120 T (°C) amb 002aad888 80 120 T (°C) amb © NXP B.V. 2010. All rights reserved ...

Page 42

... Fig 37. Temperature error versus power supply noise frequency Rev. 01 — 27 January 2010 002aad890 amb 002aad892 noise frequency (Hz 150 mV (p-p); 0.1 μF AC coupling DD amb © NXP B.V. 2010. All rights reserved. SE97B 120 (° ° ...

Page 43

... NXP Semiconductors 3.0 T lim(acc) (°C) 1.5 0 −1.5 −3.0 − Fig 38. SE97B temperature accuracy SE97B_1 Product data sheet DDR memory module temp sensor with integrated SPD 002aaf189 120 thermal response (%) 120 0 T (°C) amb From 25 °C (air) to 120 °C (oil bath) at 3.3 V. ...

Page 44

... SCL signal) to bridge the IH(min) SE97B 2 C-bus from DC Unit Max [1] 400 kHz - 300 ns - 300 900 250 ns μ ...

Page 45

... DDR memory module temp sensor with integrated SPD t LOW HD;STA HIGH SU;STA t t HD;DAT SU;DAT t W write cycle Rev. 01 — 27 January 2010 t SU;STO t HD;DAT SU;STA START condition 002aae750 © NXP B.V. 2010. All rights reserved. SE97B ...

Page 46

... 0.30 2.1 1.6 3.1 1.6 0.25 2.0 1.5 3.0 1.5 0.5 1.5 0.18 1.9 1.4 2.9 1.4 References JEDEC JEITA - - - MO-229 Rev. 01 — 27 January 2010 detail 0.40 0.45 0.35 0.40 0.1 0.05 0.05 0.05 0.30 0.35 European projection SE97B SOT1069 sot1069-2_po Issue date 09-10-22 09-11-18 © NXP B.V. 2010. All rights reserved ...

Page 47

... Solder bath specifications, including temperature and impurities SE97B_1 Product data sheet DDR memory module temp sensor with integrated SPD Rev. 01 — 27 January 2010 SE97B © NXP B.V. 2010. All rights reserved ...

Page 48

... Package reflow temperature (°C) 3 Volume (mm ) < 350 260 260 250 Figure 42. Rev. 01 — 27 January 2010 Figure 42) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 245 245 245 © NXP B.V. 2010. All rights reserved. SE97B ...

Page 49

... Electrically Erasable Programmable Read-Only Memory ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Least Significant Bit Machine Model Most Significant Bit Personal Computer Printed-Circuit Board Power-On Reset Rev. 01 — 27 January 2010 SE97B peak temperature time 001aac844 © NXP B.V. 2010. All rights reserved ...

Page 50

... DDR memory module temp sensor with integrated SPD Abbreviations …continued Description System Management Bus Small Outline Dual In-line Memory Module Serial Presence Detect Data sheet status Product data sheet Rev. 01 — 27 January 2010 SE97B Change notice Supersedes - - © NXP B.V. 2010. All rights reserved ...

Page 51

... Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com Rev. 01 — 27 January 2010 SE97B © NXP B.V. 2010. All rights reserved ...

Page 52

... MANID — Manufacturer’s ID register (06h, 16-bit read-only 8.8 DEVICEID — Device ID register (07h, 16-bit read-only 8.9 SMBUS — SMBus register (22h, 8-bit read/write Application design-in information 9.1 SE97B in memory module application . . . . . . 36 9.2 Layout consideration . . . . . . . . . . . . . . . . . . . 36 9.3 Thermal considerations . . . . . . . . . . . . . . . . . 36 9.4 Hot plugging Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 38 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38 12 Package outline ...

Page 53

... Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com SE97B All rights reserved. Date of release: 27 January 2010 Document identifier: SE97B_1 ...

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