hcs573ms Intersil Corporation, hcs573ms Datasheet
hcs573ms
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hcs573ms Summary of contents
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... Output Enable. The HCS573MS utilizes advanced CMOS/SOS technology to achieve high-speed operation. This device is a member of radiation hardened, high-speed, CMOS/SOS Logic Family. The HCS573MS is supplied lead Ceramic flatpack (K suffi SBDIP Package (D suffix). Ordering Information PART NUMBER ...
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... OUTPUT ENABLE High Level L = Low Level X = Immaterial Z = High Impedance I = Low voltage level prior to the high-to-low latch enable transition h = High voltage level prior to the high-to-low latch enable transition HCS573MS TRUTH TABLE LATCH ENABLE ...
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... Functional Test VIH = 0.70(VCC), VIL = 0.30(VCC) (Note 2) NOTES: 1. All voltages reference to device GND. 2. For functional tests VO 4.0V is recognized as a logic “1”, and VO Specifications HCS573MS Reliability Information Thermal Resistance SBDIP Package 10mA Ceramic Flatpack Package . . . . . . . . . . . 25mA Maximum Package Power Dissipation at +125 SBDIP Package ...
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... The parameters listed in Table 3 are controlled via design or process parameters. Min and Max Limits are guaranteed but not directly tested. These parameters are characterized upon initial design release and upon design changes which affect these characteristics. Specifications HCS573MS GROUP (NOTES 1, 2) ...
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... AC measurements assume RL = 500 , CL = 50pF, Input 3ns, VIL = GND, VIH = VCC. 3. For functional tests VO 4.0V is recognized as a logic “1”, and VO TABLE 5. BURN-IN AND OPERATING LIFE TEST, DELTA PARAMETERS (+25 PARAMETER ICC IOL/IOH IOZL/IOZH Specifications HCS573MS (NOTES 1, 2) CONDITIONS TEMPERATURE 0.5V is recognized as a logic “0”. GROUP B SUBGROUP DELTA LIMIT ...
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... Each pin except VCC and GND will have a resistor of 680 OPEN NOTE: Each pin except VCC and GND will have a resistor of 47K Group E, Subgroup 2, sample size is 4 dice/wafer 0 failures. Specifications HCS573MS TABLE 6. APPLICABLE SUBGROUPS METHOD GROUP A SUBGROUPS 100%/5004 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com HCS573MS 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% Static Burn-In 2, Condition hrs ...
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... DATA VS VS TPLH QN VS FIGURE 1. LATCH ENABLE PROPAGATION DELAYS TTLH VOH 80% 20% OUTPUT VOL FIGURE 3. DATA SET-UP AND HOLD TIMES AC Load Circuit HCS573MS INPUT LEVEL DATA VS TH( TPHL QN VS FIGURE 2. LATCH ENABLE PREREQUISITE TIMES PARAMETER VCC VIH TTHL VS 80% 20% ...
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... VIH INPUT VS VIL TPZH VOH VT OUTPUT VOZ THREE-STATE HIGH VOLTAGE LEVELS PARAMETER HCS VCC 4.50 VIH 4.50 VS 2.25 VT 2.25 VW 3.60 GND 0 HCS573MS Three-State Low Load Circuit TPLZ VW UNITS Three-State High Load Circuit DUT TPHZ CL = 50pF 500 UNITS 332 ...
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... Thickness: 13k 2.6k WORST CASE CURRENT DENSITY <2 A/cm BOND PAD SIZE: 100 m x 100 mils Metallization Mask Layout D1 (3) D2 (4) D3 (5) D4 (6) D5 (7) D6 (8) (9) D7 HCS573MS HCS573MS D0 OE VCC Q0 (2) (1) (20) (19) (10) (11) (12) GND LE Q7 333 (18) Q1 (17) Q2 (16) Q3 (15) Q4 ...