pxf4336 Infineon Technologies Corporation, pxf4336 Datasheet - Page 334
pxf4336
Manufacturer Part Number
pxf4336
Description
Abm Premium Atm Buf Fer Manager
Manufacturer
Infineon Technologies Corporation
Datasheet
1.PXF4336.pdf
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Register 97 ERCM1
CPU Accessibility:
Reset Value:
Offset Address:
Typical Usage:
Bit
Bit
ERCM1(31:16)
Data Sheet
15
7
AVT Table Access Mask Register 1
14
ERC Mask Register 1
ERC Mask Registers 0..1 control the Write access from transfer
registers ERCT0 and ERCT1 to the internal AVT table on a per-bit
selection basis. The mask register bit positions correspond to the
respective transfer registers ERCT0 and ERCT1:
0
1
6
Read/Write
0000
ERCM0
Written by CPU to control internal table Read/Write
access
H
13
5
The dedicated bit of the transfer register overwrites the
table entry during Write.
Does not affect Read access.
The dedicated bit of the transfer register does not
overwrite the table entry during Write.
Does not affect Read access.
CD
ERCM1(31:24)
ERCM1(23:16)
H
12
4
334
11
3
10
2
Register Description
PXF 4336 V1.1
9
1
2001-12-17
ABM-P
8
0
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