attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 101

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

EEPROM Write Prevents
Writing to SPMCSR
Reading the Fuse and Lock
Bits from Software
2535G–AVR–01/07
Note that an EEPROM write operation will block all software programming to Flash.
Reading the Fuses and Lock bits from software will also be prevented during the
EEPROM write operation. It is recommended that the user checks the status bit (EEPE)
in the EECR Register and verifies that the bit is cleared before writing to the SPMCSR
Register.
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits,
load the Z-pointer with 0x0001 and set the RFLB and SELFPRGEN bits in SPMCSR.
When an LPM instruction is executed within three CPU cycles after the RFLB and
SELFPRGEN bits are set in SPMCSR, the value of the Lock bits will be loaded in the
destination register. The RFLB and SELFPRGEN bits will auto-clear upon completion of
reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no
SPM instruction is executed within four CPU cycles. When RFLB and SELFPRGEN are
cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for
reading the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and
set the RFLB and SELFPRGEN bits in SPMCSR. When an LPM instruction is executed
within three cycles after the RFLB and SELFPRGEN bits are set in the SPMCSR, the
value of the Fuse Low byte (FLB) will be loaded in the destination register as shown
below. Refer to Table 45 on page 104 for a detailed description and mapping of the
Fuse Low byte.
Similarly, when reading the Fuse High byte, load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the RFLB and SELFPRGEN bits are set
in the SPMCSR, the value of the Fuse High byte (FHB) will be loaded in the destination
register as shown below. Refer to Table 44 on page 104 for detailed description and
mapping of the Fuse High byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that
are unprogrammed, will be read as one.
Bit
Rd
Bit
Rd
Bit
Rd
FHB7
FLB7
7
7
7
–
FHB6
FLB6
6
6
6
–
FHB5
FLB5
5
5
5
–
FHB4
FLB4
4
–
4
4
FLB3
FHB3
3
–
3
3
FHB2
FLB2
2
–
2
2
FHB1
FLB1
LB2
1
1
1
FHB0
FLB0
LB1
0
0
0
101