attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 16

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

EEPROM Control Register –
EECR
16
ATtiny13
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use and will always read as 0 in ATtiny13. For compatibility
with future AVR devices, always write this bit to zero. After reading, mask out this bit.
• Bit 6 – Res: Reserved Bit
This bit is reserved in the ATtiny13 and will always read as zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bits setting defines which programming action that
will be triggered when writing EEPE. It is possible to program data in one atomic opera-
tion (erase the old value and program the new value) or to split the Erase and Write
operations in two different operations. The Programming times for the different modes
are shown in Table 1. While EEPE is set, any write to EEPMn will be ignored. During
reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.
Table 1. EEPROM Mode Bits
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set.
Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a
constant interrupt when Non-volatile memory is ready for programming.
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at
the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE
has been written to one by software, hardware clears the bit to zero after four clock
cycles.
• Bit 1 – EEPE: EEPROM Program Enable
The EEPROM Program Enable Signal EEPE is the programming enable signal to the
EEPROM. When EEPE is written, the EEPROM will be programmed according to the
EEPMn bits setting. The EEMPE bit must be written to one before a logical one is writ-
ten to EEPE, otherwise no EEPROM write takes place. When the write access time has
elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is
halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When
the correct address is set up in the EEARL Register, the EERE bit must be written to
Bit
Read/Write
Initial Value
EEPM1
0
0
1
1
EEPM0
0
1
0
1
R
7
–
0
Programming
6
–
R
0
3.4 ms
1.8 ms
1.8 ms
Time
–
EEPM1
R/W
X
5
Operation
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
Reserved for future use
EEPM0
R/W
X
4
EERIE
R/W
3
0
EEMPE
R/W
2
0
EEPE
R/W
X
1
EERE
R/W
0
0
2535G–AVR–01/07
EECR