attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 28

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

Idle Mode
ADC Noise Reduction
Mode
Power-down Mode
28
ATtiny13
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter
Idle mode, stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter,
Watchdog, and the interrupt system to continue operating. This sleep mode basically
halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt
is not required, the Analog Comparator can be powered down by setting the ACD bit in
the Analog Comparator Control and Status Register – ACSR. This will reduce power
consumption in Idle mode. If the ADC is enabled, a conversion starts automatically
when this mode is entered.
When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter
ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external inter-
rupts, and the Watchdog to continue operating (if enabled). This sleep mode halts clk
clk
This improves the noise environment for the ADC, enabling higher resolution measure-
ments. If the ADC is enabled, a conversion starts automatically when this mode is
entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a
Watchdog Reset, a Brown-out Reset, an SPM/EEPROM ready interrupt, an external
level interrupt on INT0 or a pin change interrupt can wake up the MCU from ADC Noise
Reduction mode.
When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the Oscillator is stopped, while the external interrupts,
and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog
Reset, a Brown-out Reset, an external level interrupt on INT0, or a pin change interrupt
can wake up the MCU. This sleep mode halts all generated clocks, allowing operation of
asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to “External Inter-
rupts” on page 54 for details.
Table 11. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Note:
Sleep Mode
Idle
ADC Noise
Reduction
Power-down
CPU
, and clk
CPU
1. For INT0, only level interrupt.
and clk
FLASH
Active Clock Domains
FLASH
, while allowing the other clocks to run.
, while allowing the other clocks to run.
X
X
X
Oscillators
X
X
X
X
X
(1)
(1)
Wake-up Sources
X
X
X
X
2535G–AVR–01/07
X
X
X
X
I/O
,