attiny13-20ss ATMEL Corporation, attiny13-20ss Datasheet - Page 56

• Manufacturer Part Number: attiny13-20ss
• Description: 8-bit Microcontroller With 1k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

General Interrupt Mask
Register – GIMSK
General Interrupt Flag
Register – GIFR
56
ATtiny13
• Bits 7, 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU Control Register (MCUCR) define whether the external interrupt is
activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin
will cause an interrupt request even if INT0 is configured as an output. The correspond-
ing interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE: Pin Change Interrupt Enable
When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
pin change interrupt is enabled. Any change on any enabled PCINT5..0 pin will cause
an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI Interrupt Vector. PCINT5..0 pins are enabled individually by the PCMSK0
Register.
• Bits 7, 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny13 and will always read as zero.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0
becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the
MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the inter-
rupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to
it. This flag is always cleared when INT0 is configured as a level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When a logic change on any PCINT5..0 pin triggers an interrupt request, PCIF becomes
set (one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will
jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
R
7
–
0
7
–
0
INTF0
INT0
R/W
R/W
6
0
6
0
PCIE
PCIF
R/W
R/W
5
0
5
0
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
R
R
2
–
0
2
–
0
R
R
1
–
0
1
–
0
R
R
2535G–AVR–01/07
0
–
0
0
–
0
GIMSK
GIFR