atmega103 ATMEL Corporation, atmega103 Datasheet - Page 18

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

I/O Memory
18
ATmega103(L)
The internal Data SRAM access is performed in two System Clock cycles as described
in Figure 22.
Figure 22. On-chip Data SRAM Access Cycles
See “Interface to External SRAM” on page 84. for a description of the access to the
external SRAM.
The I/O space definition of the ATmega103(L) is shown in Table 2.
Table 2. ATmega103(L) I/O Space
I/O Address (SRAM
System Clock Ø
$3E ($5E)
$3D ($5D)
$3C ($5C)
$3B ($5B)
$3A ($5A)
$2E ($4E)
$3F ($5F)
$2F ($4F)
Address)
$39 ($59)
$38 ($58)
$37 ($57)
$36 ($56)
$35 ($55)
$34 ($54)
$33 ($53)
$32 ($52)
$31 ($51)
$30 ($50)
Address
Data
Data
WR
RD
Prev. Address
Name
SREG
SPH
SPL
XDIV
RAMPZ
EICR
EIMSK
EIFR
TIMSK
TIFR
MCUCR
MCUSR
TCCR0
TCNT0
OCR0
ASSR
TCCR1A
TCCR1B
T1
Function
Status REGister
Stack Pointer High
Stack Pointer Low
XTAL Divide Control Register
RAM Page Z Select Register
External Interrupt Control Register
External Interrupt MaSK Register
External Interrupt Flag Register
Timer/Counter Interrupt MaSK Register
Timer/Counter Interrupt Flag Register
MCU General Control Register
MCU Status Register
Timer/Counter0 Control Register
Timer/Counter0 (8-bit)
Timer/Counter0 Output Compare Register
Asynchronous Mode Status Register
Timer/Counter1 Control Register A
Timer/Counter1 Control Register B
Address
T2
T3
T4
0945I–AVR–02/07