atmega103 ATMEL Corporation, atmega103 Datasheet - Page 23

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

XTAL Divide Control Register
– XDIV
Reset and Interrupt
Handling
0945I–AVR–02/07
• Bits 4, 3 – SM1/SM0: Sleep Mode Select Bits 1 and 0
This bit selects between the three available sleep modes as shown in Table 3.
Table 3. Sleep Mode Select
• Bits 2..0 – Res: Reserved Bits
These bits are reserved bits in the ATmega103(L) and always read as zero.
The XTAL Divide Control Register is used to divide the XTAL clock frequency by a num-
ber in the range 1 - 129. This feature can be used to decrease power consumption when
the requirement for processing power is low.
• Bit 7 – XDIVEN: XTAL Divide Enable
When the XDIVEN bit is set (one), the clock frequency of the CPU and all peripherals is
divided by the factor defined by the setting of XDIV6 - XDIV0. This bit can be set and
cleared run-time to vary the clock frequency as suitable to the application.
• Bits 6..0 – XDIV6..XDIV0: XTAL Divide Select Bits 6 - 0
These bits define the division factor that applies when the XDIVEN bit is set (one). If the
value of these bits is denoted d, the following formula defines the resulting CPU clock
frequency f
The value of these bits can only be changed when XDIVEN is zero. When XDIVEN is
set to one, the value written simultaneously into XDIV6..XDIV0 is taken as the division
factor. When XDIVEN is cleared to zero, the value written simultaneously into
XDIV6..XDIV0 is rejected. As the divider divides the Master Clock Input to the MCU, the
speed of all peripherals is reduced when a division factor is used.
The ATmega103(L) provides 23 different interrupt sources. These interrupts and the
separate Reset Vector each have a separate Program Vector in the Program memory
space. All interrupts are assigned individual enable bits that must be set (one) together
with the I-bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are automatically defined as the
Reset and Interrupt Vectors. The complete list of vectors is shown in Table 4. The list
also determines the priority levels of the different interrupts. The lower the address, the
Bit
$3C ($5C)
Read/Write
Initial Value
SM1
0
0
1
1
clk
:
XDIVEN
R/W
7
0
XDIV6
R/W
6
0
SM0
XDIV5
R/W
0
1
0
1
5
0
f
CLK
XDIV4
R/W
4
0
=
------------------ -
129 d
XTAL
XDIV3
R/W
–
3
0
XDIV2
R/W
2
0
ATmega103(L)
Sleep Mode
Power-down
Power-save
Idle mode
Reserved
XDIV1
R/W
1
0
XDIV0
R/W
0
0
XDIV
23