atmega103 ATMEL Corporation, atmega103 Datasheet - Page 33

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Timer/Counter Interrupt Mask
Register – TIMSK
0945I–AVR–02/07
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Interrupt Enable
When the OCIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt (at
vector $0012) is executed if a compare match in Timer/Counter2 occurs, i.e., when the
OCF2 bit is set in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector
$0014) is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is
set in the Timer/Counter Interrupt Flag Register (TIFR).
• Bit 5 – TICIE1: Timer/Counter1 Input Capture Interrupt Enable
When the TICIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Input Capture Event interrupt is enabled. The corresponding interrupt
(at vector $0016) is executed if a capture-triggering event occurs on pin 29, PD4(IC1),
i.e., when the ICF1 bit is set in the Timer/Counter Interrupt Flag Register.
• Bit 4 – OCE1A: Timer/Counter1 Output Compare A Match Interrupt Enable
When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare A Match interrupt is enabled. The corresponding interrupt (at
vector $0018) is executed if a Compare A Match in Timer/Counter1 occurs, i.e., when
the OCF1A bit is set in the Timer/Counter Interrupt Flag Register.
• Bit 3 – OCIE1B: Timer/Counter1 Output Compare B Match Interrupt Enable
When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Compare B Match interrupt is enabled. The corresponding interrupt (at
vector $001A) is executed if a Compare B Match in Timer/Counter1 occurs, i.e., when
the OCF1B bit is set in the Timer/Counter Interrupt Flag Register.
• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable
When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector
$001C) is executed if an overflow in Timer/Counter1 occurs, i.e., when the TOV1 bit is
set in the Timer/Counter Interrupt Flag Register.
• Bit 1 – OCIE0: Timer/Counter0 Output Compare Interrupt Enable
When the OCIE0 bit is set (one) and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt (at
vector $001E) is executed if a compare match in Timer/Counter0 occurs, i.e., when the
OCF0 bit is set in the Timer/Counter Interrupt Flag Register.
Bit
$37 ($57)
Read/Write
Initial Value
OCIE2
R/W
7
0
TOIE2
R/W
6
0
TICIE1
R/W
5
0
OCIE1A
R/W
4
0
OCIE1B
R/W
3
0
TOIE1
ATmega103(L)
R/W
2
0
OCIE0
R/W
1
0
TOIE0
R/W
0
0
TIMSK
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