atmega103 ATMEL Corporation, atmega103 Datasheet - Page 62

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

Data Modes
SPI Control Register – SPCR
62
ATmega103(L)
the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI
will stop sending and receiving immediately and both data received and data sent must
be considered as lost.
There are four combinations of SCK phase and polarity with respect to serial data that
are determined by control bits CPHA and CPOL. The SPI data transfer formats are
shown in Figure 39 and Figure 40.
Figure 39. SPI Transfer Format with CPHA = 0 and DORD = 0
Figure 40. SPI Transfer Format with CPHA = 1 and DORD = 0
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set
and the Global Interrupts are enabled.
• Bit 6 – SPE: SPI Enable
When the SPE bit is set (one), the SPI is enabled and SS, MOSI, MISO and SCK are
connected to pins PB0, PB1, PB2 and PB3.
(FOR REFERENCE)
(FOR REFERENCE)
Bit
$0D ($2D)
Read/Write
Initial Value
(FROM MASTER)
(FROM MASTER)
SS (TO SLAVE)
SS (TO SLAVE)
(FROM SLAVE)
(FROM SLAVE)
SCK (CPOL=0)
SCK (CPOL=1)
SCK (CPOL=0)
SCK (CPOL=1)
SCK CYCLE #
SCK CYCLE #
SAMPLE
SAMPLE
MOSI
MISO
MOSI
MISO
SPIE
R/W
7
0
* Not defined but normally MSB of character just received.
* Not defined but normally LSB of previously transmitted character.
SPE
R/W
*
6
0
MSB
MSB
1
MSB
MSB
1
DORD
R/W
5
0
2
6
6
2
6
6
MSTR
R/W
3
4
0
3
5
5
5
5
4
CPOL
4
4
4
R/W
4
4
3
0
5
5
3
3
3
3
CPHA
R/W
2
0
6
6
2
2
2
2
SPR1
R/W
1
0
7
7
1
1
1
1
SPR0
8
LSB
LSB
8
R/W
LSB
0
0
0945I–AVR–02/07
LSB
SPCR
*