atmega103 ATMEL Corporation, atmega103 Datasheet - Page 81

• Manufacturer Part Number: atmega103
• Description: Atmega103 8-bit With 128k Bytes Of In-system Programmable Flash
• Manufacturer: ATMEL Corporation

ADC Data Register – ADCL
and ADCH
0945I–AVR–02/07
• Bit 5 – Res: Reserved Bit
This bit is reserved in the ATmega103(L). Warning: When writing ADCSR, a logical “0”
must be written to this bit.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set (one) when an ADC conversion is complete and the result is written to the
ADC Data Registers are updated. The ADC Conversion Complete interrupt is executed
if the ADIE bit and the I-bit in SREG are set (one). ADIF is cleared by hardware when
executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by
writing a logical “1” to the flag. Beware that if doing a Read-Modify-Write on ADCSR, a
pending interrupt can be disabled. This also applies if the SBI and CBI instructions are
used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com-
plete interrupt is activated.
• Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits
These bits determine the division factor between the XTAL frequency and the input
clock to the ADC.
Table 27. ADC Prescaler Selections
When an ADC conversion is complete, the result is found in these two registers. It is
essential that both registers are read and that ADCL is read before ADCH.
Bit
$05 ($25)
$04 ($24)
Read/Write
Initial Value
ADPS2
0
0
0
0
1
1
1
1
ADC7
15
R
R
–
7
0
0
ADC6
ADPS1
14
R
R
–
6
0
0
0
0
1
1
0
0
1
1
ADC5
13
R
R
–
5
0
0
ADC4
12
R
R
–
4
0
0
ADPS0
0
1
0
1
0
1
0
1
ADC3
11
–
3
R
R
0
0
ADC2
10
R
R
–
2
0
0
ATmega103(L)
ADC9
ADC1
Division Factor
R
R
9
1
0
0
Invalid
128
16
32
64
2
4
8
ADC8
ADC0
R
R
8
0
0
0
ADCH
ADCL
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