atmega603 ATMEL Corporation, atmega603 Datasheet - Page 8

• Manufacturer Part Number: atmega603
• Description: 8-bit Microcontroller With 64k/128k Bytes In-system Programmable Flash - Atmel Corporation
• Manufacturer: ATMEL Corporation

ATmega603/103 Instruction Set Summary (Continued)
8
DATA TRANSFER INSTRUCTIONS
ELPM
MOV
LDI
LD
LD
LD
LD
LD
LD
LDD
LD
LD
LD
LDD
LDS
ST
ST
ST
ST
ST
ST
STD
ST
ST
ST
STD
STS
LPM
IN
OUT
PUSH
POP
BIT AND BIT-TEST INSTRUCTIONS
SBI
CBI
LSL
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
CLI
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
NOP
SLEEP
WDR
()
ATmega603(L) and ATmega103(L)
Rd, Rr
Rd, K
Rd, X
Rd, X+
Rd, - X
Rd, Y
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
X, Rr
X+, Rr
- X, Rr
Y, Rr
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Rd, P
P , Rr
Rr
Rd
P ,b
P ,b
Rd
Rd
Rd
Rd
Rd
Rd
s
s
Rr, b
Rd, b
Extended Load Program Memory
Move Between Registers
Load Immediate
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
In Port
Out Port
Push Register on Stack
Pop Register from Stack
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
Clear T in SREG
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
No Operation
Sleep
Watchdog Reset
R0
Rd
Rd
Rd
X
Rd
Rd
Y
Rd
Rd
Rd
Rd
Rd
(X)
(X)
X
(Y)
(Y)
Y
(Z)
Z
(k)
R0
Rd
P
STACK
Rd
I/O(P ,b)
Rd(n)
Rd(0)
Rd(n)
SREG(s)
SREG(s)
T
Rd(b)
C
C
N
N
Z
Z
I
S
S
V
V
T
T
H
H
(see specific descr. for Sleep function)
(see specific descr. for WD timer)
Rd
Z
(Y + q)
(Z)
(Z + q)
I/O(P ,b)
Rd(n+1)
Rd(7)
Rd(3..0)
I
1
0
Z - 1, Rd
Z - 1, (Z)
Rr(b)
1
0
1
0
X - 1, Rd
Y - 1, Rd
X - 1, (X)
Y - 1, (Y)
Rr
1
0
1
0
1
0
1
0
1
0
Rr
(Z+RAMPZ)
Rr
(X)
(X), X
(Y)
(Y), Y
(Y + q)
(Z)
(Z), Z
(Z + q)
Rr
Rr, X
Rr
Rr, Y
Rr
Rr, Z
(Z)
P
STACK
K
(k)
C,Rd(n+1)
C,Rd(n)
Rd(n+1), Rd(7)
Rd(n+1), n=0..6
T
Rr
Rr
Rd(7..4),Rd(7..4)
Rr
1
0
Rd(n), Rd(0)
1
0
Z + 1
X + 1
Y + 1
Z+1
X + 1
Y + 1
(Z)
Rr
(X)
(Y)
Rr
Rr
Rd(n+1),C
Rd(n),C
0
0
Rd(3..0)
Rd(7)
Rd(0)
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
S
V
V
T
T
H
H
None
None
None
3
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1