dspic33fj128mc204 Microchip Technology Inc., dspic33fj128mc204 Datasheet - Page 214
dspic33fj128mc204
Manufacturer Part Number
dspic33fj128mc204
Description
High-performance, 16-bit Digital Signal Controllers
Manufacturer
Microchip Technology Inc.
Datasheet
1.DSPIC33FJ128MC204.pdf
(412 pages)
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REGISTER 16-6:
DS70291C-page 212
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-12
bit 11-8
bit 7-3
bit 2
bit 1
bit 0
U-0
U-0
—
—
Unimplemented: Read as ‘0’
SEVOPS<3:0>: PWM Special Event Trigger Output Postscale Select bits
1111 = 1:16 postscale
0001 = 1:2 postscale
0000 = 1:1 postscale
Unimplemented: Read as ‘0’
IUE: Immediate Update Enable bit
1 = Updates to the active PxDC registers are immediate
0 = Updates to the active PxDC registers are synchronized to the PWM time base
OSYNC: Output Override Synchronization bit
1 = Output overrides via the PxOVDCON register are synchronized to the PWM time base
0 = Output overrides via the PxOVDCON register occur on next T
UDIS: PWM Update Disable bit
1 = Updates from Duty Cycle and Period Buffer registers are disabled
0 = Updates from Duty Cycle and Period Buffer registers are enabled
•
•
•
U-0
U-0
—
—
PWMxCON2: PWM CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
Preliminary
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
U-0
—
R/W-0
R/W-0
IUE
SEVOPS<3:0>
CY
boundary
© 2009 Microchip Technology Inc.
x = Bit is unknown
OSYNC
R/W-0
R/W-0
R/W-0
R/W-0
UDIS
bit 8
bit 0
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