at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 187
at91cap7e
Manufacturer Part Number
at91cap7e
Description
Customizable Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.AT91CAP7E.pdf
(520 pages)
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22.7.2
Register Name:
Access Type:
Reset Value:
• COUNT: SDRAMC Refresh Timer Count
This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh
burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate
of the SDRAM device and the refresh burst length where 15.6 μs per row is a typical value for a burst of length one.
To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is
issued and no refresh of the SDRAM device is carried out.
22.7.3
Register Name:
Access Type:
Reset Value:
• NC: Number of Column Bits
8549A–CAP–10/08
DBW
31
23
15
31
23
15
–
–
–
7
7
SDRAMC Refresh Timer Register
SDRAMC Configuration Register
30
22
14
30
22
14
–
–
–
6
6
TRCD
TXSR
TRC
CAS
29
21
13
29
21
13
–
–
–
5
5
SDRAMC_TR
Read/Write
0x00000000
SDRAMC_CR
Read/Write
0x852372C0
NB
28
20
12
28
20
12
–
–
–
4
4
COUNT
27
19
11
27
19
11
–
–
3
3
NR
26
18
10
26
18
10
–
–
2
2
COUNT
TRAS
TWR
TRP
25
17
25
17
–
–
9
1
9
1
AT91CAP7E
NC
24
16
24
16
–
–
8
0
8
0
187
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