at91cap7e ATMEL Corporation, at91cap7e Datasheet - Page 342
at91cap7e
Manufacturer Part Number
at91cap7e
Description
Customizable Microcontroller
Manufacturer
ATMEL Corporation
Datasheet
1.AT91CAP7E.pdf
(520 pages)
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• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
The delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
If FDIV is 0:
If FDIV is 1:
Note:
342
N =
AT91CAP7E
32
Delay Between Consecutive Transfers
Delay Between Consecutive Transfers
Delay Between Consecutive Transfers
=
=
=
32
------------------------------------------------ -
32
------------------------------------ -
32
------------------------------------ -
×
×
×
MCK
MCK
N
DLYBCT
DLYBCT
MCK
×
DLYBCT
+
N
------------------------- -
2MCK
×
SCBR
8549A–CAP–10/08
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