at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 107

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Internal Interrupt Edge
Triggered Source
Internal Interrupt Level
Sensitive Source
Normal Interrupt
Priority Controller
1790A–ATARM–11/03
Figure 32. Internal Interrupt Edge Triggered Source
Figure 33. Internal Interrupt Level Sensitive Source
An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt
conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast
Forcing).
Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by
writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the
highest priority and level 0 the lowest.
As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SVR
(Source Vector Register), the nIRQ line is asserted. As a new interrupt condition might have
happened on other interrupt sources since the nIRQ has been asserted, the priority controller
determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read.
The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to
consider that the interrupt has been taken into account by the software.
The current priority level is defined as the priority level of the current interrupt.
If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is
read, the interrupt with the lowest interrupt source number is serviced first.
The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with
a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment
in progress, it is delayed until the software indicates to the AIC the end of the current service
by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is
the exit point of the interrupt handling.
nIRQ
MCK
nIRQ
MCK
Peripheral Interrupt
Peripheral Interrupt
Becomes Active
Becomes Active
Maximum IRQ Latency = 4.5 Cycles
Maximum IRQ Latency = 3.5 Cycles
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