at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 108

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at91rm3400

Manufacturer Part Number
at91rm3400
Description
Atmel Advanced At91 Arm Microcontroller
Manufacturer
ATMEL Corporation
Datasheet

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Interrupt Nesting
Interrupt Vectoring
Interrupt Handlers
108
AT91RM3400
The priority controller utilizes interrupt nesting in order for the highest priority interrupt to be
handled during the service of lower priority interrupts. This requires the interrupt service rou-
tines of the lower interrupts to re-enable the interrupt at the processor level.
When an interrupt of a higher priority happens during an already occurring interrupt service
routine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current
execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this
time, the current interrupt number and its priority level are pushed into an embedded hardware
stack, so that they are saved and restored when the higher priority interrupt servicing is fin-
ished and the AIC_EOICR is written.
The AIC is equipped with an 8-level wide hardware stack in order to support up to eight inter-
rupt nestings pursuant to having eight priority levels.
The interrupt handler addresses corresponding to each interrupt source can be stored in the
registers AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor
reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to
the current interrupt is returned.
This feature offers a way to branch in one single instruction to the handler corresponding to
the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus
accessible from the ARM interrupt vector at address 0x0000 0018 through the following
instruction:
When the processor executes this instruction, it loads the read value in AIC_IVR in its program
counter, thus branching the execution on the correct interrupt handler.
This feature is often not used when the application is based on an operating system (either
real time or not). Operating systems often have a single entry point for all the interrupts and
the first task performed is to discern the source of the interrupt.
However, it is strongly recommended to port the operating system on AT91 products by sup-
porting the interrupt vectoring. This can be performed by defining all the AIC_SVR of the
interrupt source to be handled by the operating system at the address of its interrupt handler.
When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a
specific very fast handler and not onto the operating system’s general interrupt handler. This
facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software
peripheral handling) to be handled efficiently and independently of the application running
under an operating system.
This section gives an overview of the fast interrupt handling sequence when using the AIC. It
is assumed that the programmer understands the architecture of the ARM processor, and
especially the processor interrupt modes and the associated status bits.
It is assumed that:
1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are
2. The instruction at the ARM interrupt exception vector address is required to work with
When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows:
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in
LDR
loaded with corresponding interrupt service routine addresses and interrupts are
enabled.
the vectoring
LDR PC, [PC, # -&F20]
the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with
PC,[PC,# -&F20]
1790A–ATARM–11/03

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