at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 110

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Fast Interrupt
Vectoring
Fast Interrupt
Handlers
110
AT91RM3400
fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sen-
sitive or low-level sensitive
Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt
Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of
AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled.
The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0).
The value written into this register is returned when the processor reads AIC_FVR (Fast Vec-
tor Register). This offers a way to branch in one single instruction to the interrupt handler, as
AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM
fast interrupt vector at address 0x0000 001C through the following instruction:
When the processor executes this instruction it loads the value read in AIC_FVR in its pro-
gram counter, thus branching the execution on the fast interrupt handler. It also automatically
performs the clear of the fast interrupt source if it is programmed in edge-triggered mode.
This section gives an overview of the fast interrupt handling sequence when using the AIC. It
is assumed that the programmer understands the architecture of the ARM processor, and
especially the processor interrupt modes and associated status bits.
Assuming that:
1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with
2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector
3. The user does not need nested fast interrupts.
When nFIQ is asserted if the bit "F" of CPSR is 0, the sequence is:
1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in
2. The ARM core enters FIQ mode.
3. When the instruction loaded at address 0x1C is executed, the program counter is
4. The previous step enables branching to the corresponding interrupt service routine. It
5. The Interrupt Handler can then proceed as required. It is not necessary to save regis-
6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four
LDR
the fast interrupt service routine address, and the interrupt source 0 is enabled.
the fast interrupt:
LDR PC, [PC, # -&F20]
the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In
the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decre-
menting it by four.
loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automati-
cally clearing the fast interrupt, if it has been programmed to be edge triggered. In this
case only, it de-asserts the nFIQ line on the processor.
is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts
are not needed.
ters R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to
R13 are banked. The other registers, R0 to R7, must be saved before being used, and
restored at the end (before the next step). Note that if the fast interrupt is programmed
to be level sensitive, the source of the interrupt must be cleared during this phase in
order to de-assert the interrupt source 0.
(with instruction SUB PC, LR, #4 for example). This has the effect of returning from
the interrupt to whatever was being executed before, loading the CPSR with the SPSR
PC,[PC,# -&F20]
1790A–ATARM–11/03