at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 209

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at91rm3400

Manufacturer Part Number
at91rm3400
Description
Atmel Advanced At91 Arm Microcontroller
Manufacturer
ATMEL Corporation
Datasheet

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Part Number:
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Inputs
Input Glitch
Filtering
1790A–ATARM–11/03
Figure 68. Output Line Timings
The level on each I/O line can be read through PIO_PDSR (Peripheral Data Status Register).
This register indicates the level of the I/O lines regardless of their configuration, whether
uniquely as an input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch filters are independently programmable on each I/O line. When the glitch
filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automat-
ically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For
pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or
may not be taken into account, depending on the precise timing of its occurrence. Thus for a
pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably fil-
tered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one
Master Clock cycle latency if the pin level change occurs before a rising edge. However, this
latency does not appear if the pin level change occurs before a falling edge. This is illustrated
in Figure 69.
The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register),
PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing
PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register
enables the glitch filter on the I/O lines.
When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripher-
als. It acts only on the value read in PIO_PDSR and on the input change interrupt detection.
The glitch filters require that the PIO Controller clock is enabled.
Figure 69. Input Glitch Filter Timing
if PIO_IFSR = 0
if PIO_IFSR = 1
Write PIO_ODSR at 1
Write PIO_ODSR at 0
PIO_PDSR
PIO_PDSR
Write PIO_CODR
Write PIO_SODR
Pin Level
MCK
PIO_ODSR
PIO_PDSR
MCK
1 cycle
APB Access
1 cycle
2 Cycles
1 cycle
APB Access
2 cycles
AT91RM3400
2 Cycles
1 cycle
1 cycle
209

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