at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 233

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Chip Selects
Clock Generation and
Transfer Delays
Figure 73. Programmable Delays
1790A–ATARM–11/03
Chip Select 1
Chip Select 2
SPCK
The Chip Select lines are driven by the SPI only if it is programmed in Master Mode. These
lines are used to select the destination peripheral. The PCSDEC field in SPI_MR (Mode Reg-
ister) selects one to four peripherals (PCSDEC = 0) or up to 15 peripherals (PCSDEC = 1).
If Variable Peripheral Select is active, the chip select signals are defined for each transfer in
the PCS field in SPI_TDR. Chip select signals can thus be defined independently for each
transfer.
If Fixed Peripheral Select is active, Chip Select signals are defined for all transfers by the field
PCS in SPI_MR. If a transfer with a new peripheral is necessary, the software must wait until
the current transfer is completed, then change the value of PCS in SPI_MR before writing new
data in SPI_TDR.
The value on the NPCS pins at the end of each transfer can be read in the SPI_RDR (Receive
Data Register).
By default, all NPCS signals are high (equal to one) before and after each transfer.
The SPI Baud rate clock is generated by dividing the Master Clock (MCK) or the Master Clock
divided by 32 (if DIV32 is set in the Mode Register) by a value between 4 and 510. The divisor
is defined in the SCBR field in each Chip Select Register. The transfer speed can thus be
defined independently for each chip select signal.
Figure 73 shows a chip select transfer change and consecutive transfers on the same chip
selects. Three delays can be programmed to modify the transfer waveforms:
•
•
•
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and
bus release time.
Delay between chip selects, programmable only once for all the chip selects by writing the
field DLYBCS in the Mode Register. Allows insertion of a delay between release of one
chip select and before assertion of a new one.
Delay before SPCK, independently programmable for each chip select by writing the field
DLYBS. Allows the start of SPCK to be delayed until after the chip select has been
asserted.
Delay between consecutive transfers, independently programmable for each chip select by
writing the field DLYBCT. Allows insertion of a delay between two transfers occurring on
the same chip select
DLYBCS
DLYBS
DLYBCT
AT91RM3400
DLYBCT
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