at91rm3400 ATMEL Corporation, at91rm3400 Datasheet - Page 253

• Manufacturer Part Number: at91rm3400
• Description: Atmel Advanced At91 Arm Microcontroller
• Manufacturer: ATMEL Corporation

Modes of
Operation
Transmitting Data
Figure 83. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
1790A–ATARM–11/03
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
DADR
DADR
DADR
Figure 82. Transfer Format
The TWI has two modes of operations:
•
•
The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In
this mode, it generates the clock according to the value programmed in the Clock Waveform
Generator Register (TWI_CWGR). This register defines the TWCK signal completely,
enabling the interface to be adapted to a wide range of clocks.
After the master initiates a Start condition, it sends a 7-bit slave address, configured in the
Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the
slave address indicates the transfer direction (write or read). If this bit is 0, it indicates a write
operation (transmit operation). If the bit is 1, it indicates a request for data read (receive
operation).
The TWI transfers require the slave to acknowledge each received byte. During the acknowl-
edge clock pulse, the master releases the data line (HIGH), enabling the slave to pull it down
in order to generate the acknowledge. The master polls the data line during this clock pulse
and sets the NAK bit in the status register if the slave does not acknowledge the byte. As with
the other status bits, an interrupt can be generated if enabled in the interrupt enable register
(TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in
the control register starts the transmission. The data is shifted in the internal shifter and when
an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see Fig-
ure 84 on page 254). The master generates a stop condition to end the transfer.
The read sequence begins by setting the START bit. When the RXRDY bit is set in the status
register, a character has been received in the receive-holding register (TWI_RHR). The
RXRDY bit is reset when reading the TWI_RHR.
The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave
address). The three internal address bytes are configurable through the Master Mode register
(TWI_MMR). If the slave device supports only a 7-bit address, the IADRSZ must be set to 0.
For slave address higher than seven bits, the user must configure the address size (IADRSZ)
and set the other slave address bits in the internal address register (TWI_IADR).
W
W
W
Master transmitter mode
Master receiver mode
A
A
A
TWD
TWCK
IADR(23:16)
IADR(15:8)
IADR(7:0)
Start
Address
A
A
A
R/W
IADR(15:8)
IADR(7:0)
DATA
Ack
A
A
A
Data
IADR(7:0)
P
DATA
Ack
A
A
Data
AT91RM3400
P
DATA
Ack
Stop
A
P
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