m30833fjgp Renesas Electronics Corporation., m30833fjgp Datasheet - Page 346
m30833fjgp
Manufacturer Part Number
m30833fjgp
Description
Renesas 16/32-bit Single-chip Microcomputer M16c Family / M32c/80 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.M30833FJGP.pdf
(527 pages)
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M
R
R
e
E
3
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J
2
Figure 21. 51 Transmit and Receive Operation (16-bit Length)
0
C
1
9
3 .
8 /
B
0
1
3
Base Timer 3
ISCLK3 pin output
(transmit clock in the
channel 2 WG function)
ISTxD3 pin output
(data to be transmitted)
SIO3TR bit
when IRS=0
(no data in the
transmit buffer)
SIO3TR bit
when IRS=1
(transmission completed)
ISRxD3 pin input
(received data)
SIO3RR bit
0
3
G
J
The above timing applies under the following settings.
4
a
o r
0 -
n
• The CKDIR bit in the G3MR register is set to "0" (internal clock)
• The UFORM bit in the G3MR register is set to "0" (LSB first)
• The IPOL bit and OPOL bit in the G3CR register are set to "0" (no inverse)
• The TLD bit in the G3CR register is set to "1" (16 bits long)
3 .
u
1
p
, 1
3
1
(
2
M
0
3
0
2
6
C
Write to the G3TB register
m
n+2
8 /
Page 323
, 3
M
3
2
C
f o
8 /
Write "0" by program
if setting to "0"
4
3
Bit 0
Bit 0
The base timer is reset by the channel 0
waveform generation function
8
) T
8
Bit 1
Bit 1
21. Intelligent I/O (Group 3 Communication Function)
Bit 2
Bit 2
Bit 14
Bit 14
Write "0" by program if setting to "0"
n : Setting value of the G3PO0 register
m : Setting value of the G3PO2 register
SIO3TR bit : Bit in the IIO10IR register
SIO3RR bit : Bit in the IIO9IR register
IRS bit
: Bit in the G3MR register
Bit 15
Bit 15
Write "0" by program
if setting to "0"
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