km416c1204c Samsung Semiconductor, Inc., km416c1204c Datasheet - Page 8

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km416c1204c

Manufacturer Part Number
km416c1204c
Description
1m X 16bit Cmos Dynamic Ram With Extended Data Out
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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KM416C1004C, KM416C1204C
KM416V1004C, KM416V1204C
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
t
t
t
t
t
t
t
t
If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going.
If CAS goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going.
If
For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed
within 64ms/16ms before and after self refresh, in order to meet refresh specification.
For distributed CAS-before-RAS with 15.6us interval, CAS-before-RAS refresh should be executed with in 15.6us immediately
before and after self refresh in order to meet refresh specification.
ASC
CP
CWD
CWL
CSR
CHR
DS,
ASC
t
RASS
is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
t
, t
DH
is referenced to the earlier CAS falling edge before RAS transition low.
is specified from W falling edge to the earlier CAS rising edge.
is referenced to the later CAS rising edge after RAS transition low.
is referenced to the later CAS falling edge at word read-modify-write cycle.
6ns, assume t
CAH
UCAS
LCAS
is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)
RAS
100us, then RAS precharge time must use
are referenced to the earlier CAS falling edge.
T
=2.0ns.
t
CSR
t
RPS
t
CHR
instead of
t
RP
.
CMOS DRAM

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