x40626 Intersil Corporation, x40626 Datasheet - Page 14
x40626
Manufacturer Part Number
x40626
Description
Dual Voltage Cpu Supervisor With 64k Serial Eeprom
Manufacturer
Intersil Corporation
Datasheet
1.X40626.pdf
(23 pages)
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Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible
– SDA pin is in the input mode.
– RESET Signal is active for t
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
– A three step sequence is required before writing into
– The WP pin, when held HIGH, and WPEN bit at logic
X40626
Figure 15. X40626 Addressing
REV 1.1.15 2/11/04
to write to the device.
prior to the stop bit in order to start a nonvolatile write
cycle.
the Control Register to change Watchdog Timer or
Block Lock settings.
HIGH will prevent all writes to the Control Register.
A15
D7
A7
1
PURST
Device Identifier
A14
D6
A6
0
.
A13
A5
D5
1
Low Order Word Address
Word Address Byte 1
Word Address Byte 0
Slave Address Byte
A12
A4
D4
Data Byte
0
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High Order Word Address
A11
D3
A3
0
– Communication to the device is inhibited while
– Block Lock bits can protect sections of the memory
Symbol Table
RESET is active and any in-progress communication
is terminated.
array from write operations.
Device Select
A10
A2
S1
D2
WAVEFORM
S0
A9
A1
D1
R/W
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
A8
A0
D0
Characteristics subject to change without notice.
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
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