ak5366 AKM Semiconductor, Inc., ak5366 Datasheet

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ak5366

Manufacturer Part Number
ak5366
Description
24-bit 48khz ?? Adc With Selector/pga/alc
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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ASAHI KASEI
AK5366 is a high-performance 24-bit, 48kHz sampling ADC for consumer audio and digital recording
applications. Thanks to AKM’s Enhanced Dual-Bit modulator architecture, this analog-to-digital converter
has an impressive dynamic range of 103dB with a high level of integration. The AK5366 has a 5-channel
stereo input selector, an input Programmable Gain Amplifier with an ALC function. All this integration with
high-performance makes the AK5366 well suited for CD and DVD recording systems.
MS0309-E-00
1. 24bit Stereo ADC
2. 3-wire Serial µP Interface / I
3. Master / Slave Mode
4. Master Clock : 256fs/384fs/512fs
5. Sampling Rate : 32kHz to 48kHz
6. Power Supply
7. Ta = −40 ∼ 85°C
8. Package : 44pin LQFP
9. AK5365 Semi-Pin Compatible
• 5ch Stereo Inputs Selector
• Input PGA from +18dB to 0dB, 0.5dB Step
• Peak Hold Function
• Auto Level Control (ALC) Circuit
• Digital HPF for offset cancellation (fc=1.0Hz@fs=48kHz)
• Digital Attenuator from +8dB to −63dB, Mute
• Soft Mute
• Single-end Inputs
• S/(N+D) : 94dB
• DR, S/N : 103dB
• Audio I/F Format : 24bit MSB justified, I
• AVDD: 4.75 ∼ 5.25V (typ. 5.0V)
• DVDD: 3.0 ∼ 5.25V (typ. 3.3V)
• TVDD: 3.0 ∼ 5.25V for input tolerant (typ. 5.0V)
24-Bit 48kHz ∆Σ ADC with Selector/PGA/ALC
2
C-Bus
GENERAL DESCRIPTION
FEATURES
- 1 -
2
S
AK5366
[AK5366]
2004/05

Related parts for ak5366

ak5366 Summary of contents

Page 1

... AK5366 is a high-performance 24-bit, 48kHz sampling ADC for consumer audio and digital recording applications. Thanks to AKM’s Enhanced Dual-Bit modulator architecture, this analog-to-digital converter has an impressive dynamic range of 103dB with a high level of integration. The AK5366 has a 5-channel stereo input selector, an input Programmable Gain Amplifier with an ALC function. All this integration with high-performance makes the AK5366 well suited for CD and DVD recording systems ...

Page 2

... Pre-Amp RIN3 RIN4 RIN5 ROPIN ROUT MS0309-E-00 M/S SEL2 SEL1 SEL0 IPGAL IPGA (ALC) ADC IPGA (ALC) IPGAR SMUTE Block diagram - 2 - [AK5366] PDN I2C AVDD AVSS DVDD DVSS LRCK HPF DATT BICK Audio I/F Controller MCLK Peak SDTO Hold TVDD Control Register VCOM ...

Page 3

... TEST1 2 LIN4 3 TEST2 4 LIN3 5 TEST3 6 LIN2 7 TEST4 8 LIN1 9 LOPIN 10 LOUT MS0309-E-00 −40 ∼ +85°C 44pin LQFP (0.8mm pitch) Evaluation Board for AK5366 AK5366VQ Top View [AK5366 ] 33 CSN/CAD1 32 CCLK/SCL 31 CDTI/SDA 30 SEL2 29 SEL1 28 SEL0 ...

Page 4

... ATTR4 PHL7 PHL6 PHL5 PHL4 PHL15 PHL14 PHL13 PHL12 PHR7 PHR6 PHR5 PHR4 PHR15 PHR14 PHR13 PHR12 - 4 - [AK5366 ] AK5366 TVDD I2C max. 48kHz “1” : ALC=ON “8EH” : +7.0dB 0dB ∼ +18dB −63dB ∼ +8dB Yes Yes 400kHz Yes ...

Page 5

... Digital Power Supply Pin, 3.0 ∼ 5.25V 20 DVDD - 21 SDTO O Audio Serial Data Output Pin 22 BICK I/O Audio Serial Data Clock Pin Note: All digital input pins except pull-down pins should not be left floating. Note: TEST1, TEST2, TEST3 and TEST4 pins should be connected to AVSS. MS0309-E-00 PIN/FUNCTION Function - 5 - [AK5366 ] 2004/05 ...

Page 6

... C Control 2 C Control 2 C Control 2 C Control , “L” : 3-wire Control “L” : Slave Mode - 6 - [AK5366 ] (I2C pin = “L”) (I2C pin = “H”) (I2C pin = “L”) (I2C pin = “H”) (I2C pin = “L”) (I2C pin = “H”) 2004/05 ...

Page 7

... ROPIN/ROUT SMUTE SEL2-0 CSN Digital CCLK/SCL CDTI/SDA I2C MS0309-E-00 Setting These pins should be open. Connected 10kΩ resistor between LOPIN pin and LOUT pin. Connected 10kΩ resistor between ROPIN pin and ROUT pin. These pins should be connected to DVSS [AK5366 ] 2004/05 ...

Page 8

... WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0309-E-00 ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD (Note 2) TVDD ∆GND (Note 3) IIN (Note 4) VINA VIND1 VIND2 Ta Tstg Symbol min AVDD 4.75 DVDD 3.0 TVDD DVDD - 8 - [AK5366 ] min max Units −0.3 6.0 V −0.3 6.0 V −0.3 6 0.3 V ± −0.3 AVDD+0.3 V −0.3 DVDD+0.3 V −0.3 TVDD+0 ...

Page 9

... Note 13. All digital input pins are held DVSS. MS0309-E-00 ANALOG CHARACTERISTICS min 10 (Note 6) - (Note 6) - (Note 7) 6.3 (Note 8) 0.9 (Note 9) 6.3 0.2 0 −9.5 (Note 10 (Note 11) 90 (Note 12) (Note 13 [AK5366 ] typ max Units 50 kΩ 100 dB 108 dB kΩ 1.1 Vrms 10 15 kΩ 0.5 0.8 dB + ...

Page 10

... SB 26 ∆ CHARACTERISTICS Symbol min (Note 16) VIH 70%DVDD (Note 16) VIL - (Note 17) VAC 50%DVDD VOH DVDD−0.5 VOL - VOL - (Note 18) Iin - - 10 - [AK5366 ] typ max Units 21.5 kHz 21.768 - kHz 22.0 - kHz 24.0 - kHz kHz ±0.005 1/fs µs 0 1.0 Hz 2.9 Hz 6.5 Hz typ max ...

Page 11

... S mode) tLRS tBSD fBCK dBCK −20 tMBLR −20 tBSD - 11 - [AK5366 ] typ max Units 24.576 MHz kHz 64fs ...

Page 12

... CSN “↑” to SDTO valid Note 21. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 22. The AK5366 can be reset by bringing the PDN pin = “L”. Note 23. This cycle is the number of LRCK rising edges from the PDN pin = “H”. ...

Page 13

... BICK tBCKH 1000pF MCLK Input MCLK AC Coupling Timing (Measurement condition) *Refer to Figure 2 for input circuit example. MS0309-E-00 1/fCLK tCLKL 1/fs tBCK tBCKL Clock Timing Measurement Point 100kΩ AGND AGND - 13 - [AK5366 ] VIH VIL VIH VIL VIH VIL 1/fCLK tACW tACW VAC 2004/05 ...

Page 14

... CDTI MS0309-E-00 tLRB tBSD Audio Interface Timing (Slave mode) dBCK tBSD Audio Interface Timing (Master mode) tCSS tCCKL tCCKH tCDS C1 C0 WRITE Command Input Timing - 14 - [AK5366 ] VIH VIL VIH VIL 50%DVDD 50%DVDD 50%DVDD 50%DVDD VIH VIL VIH VIL tCDH VIH R/W VIL ...

Page 15

... D1 D0 WRITE Data Input Timing tHIGH tF tHD:DAT tSU:DAT tSU:STA Start Bus Mode Timing tPDV tPDV tPD Power Down & Reset Timing - 15 - [AK5366 ] tCSW VIH VIL VIH VIL VIH VIL VIH VIL tSP VIH VIL tSU:STO Stop VIH VIL 50%DVDD ...

Page 16

... AK5366 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK5366 in power-down mode (PDN pin = “L” or PWN bit = “0”). In master mode, the master clock (MCLK) must be provided unless PDN pin = “L”. ...

Page 17

... MCKAC = "1" MCKPD = "0" AK5366 SDTO LRCK BICK ≥ 48fs (Slave) H/L 64fs (Master) ≥ 48fs (Slave Compatible L/H 64fs (Master) Table 4. Audio Interface Format - 17 - [AK5366 ] MCKAC bit MCKPD bit Don’t care Figure Figure 3 Default Figure 4 2004/05 ...

Page 18

... Master Mode and Slave Mode The M/S pin selects either master or slave mode. M/S pin = “H” selects master mode and “L” selects slave mode. The AK5366 outputs BICK and LRCK in master mode. In slave mode, MCLK, BICK and LRCK are input externally. Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation ...

Page 19

... ASAHI KASEI Power-up/down The AK5366 is placed in the power-down mode by bringing PDN pin = “L” and the digital filter is also reset at the same time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after 516 cycles of LRCK. ...

Page 20

... The AK5366 includes 5ch stereo input selectors (Figure 6). The input selector selector. The input channel is set by the SEL2-0 bits (Table 6) and the SEL2-0 pins (Table 7). The SEL2-0 pins should be fixed to “LLL” if the AK5366 is controlled by the SEL 2-0 bits, because the setting of the SEL2-0 pins are prior to the SEL2-0 bits setting. ...

Page 21

... The period of (1) varies in the setting value of DATT. It takes 1028/fs to mute when DATT value is +8dB. When changing channels, the input channel should be changed during (2). The period of (2) should be around 200ms because there is some DC difference between the channels. MS0309-E-00 (1) (2) LIN 1 LIN 2 [AK5366 ] (1) 2004/05 ...

Page 22

... LOPIN LOUT LIN1 LIN2 LIN3 LIN4 Pre-Amp LIN5 RIN1 RIN2 Pre-Amp RIN3 RIN4 RIN5 ROPIN ROUT Rf Figure 8. Input ATT ATT Gain [dB] Rf [kΩ] −11.86 12 −5. Table 8. Input ATT example - 22 - [AK5366 ] IPGAL To IPGA To IPGA IPGAR IPGAL/R pin 1.02Vrms 1.02Vrms 1Vrms 2004/05 ...

Page 23

... ASAHI KASEI Input Volume The AK5366 includes two independent channel analog volumes (IPGA) with 37 levels at 0.5dB steps located in front of the ADC. The IPGA is a true analog volume control that improves the S/N ratio as seen in Table 9. Independent zero-crossing detection is used to ensure level changes only occur during zero-crossings. If there are no zero-crossings, the level will then change after a time-out period (Table 10) ...

Page 24

... ALC operation. [2] ALC Recovery Operation The ALC recovery refers to the amount of time that the AK5366 will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC limiter operation. If the input signal does not exceed the “ ...

Page 25

... Figure 9. ALC Level diagram example (ALC=OFF) In Figure 10, Input ATT is −6dB. Input 2Vrms 1Vrms 0.5Vrms Figure 10. ALC Level diagram example (ALC=OFF) MS0309-E-00 ATT IPGA ADC -12dB -12dB +6dB +12dB ATT IPGA ADC -6dB -6dB -6dB +6dB -6dB +12dB - 25 - [AK5366 ] 0dBFS 0dBFS 2004/05 ...

Page 26

... Figure 12. ALC Level diagram example (ALC=ON, LMTH=“0”) MS0309-E-00 ATT ALC ADC -12dB -12dB -0.5dB +5.5dB -12dB +6dB ATT ALC ADC -6dB -6dB -0.5dB -6dB +5.5dB -6dB +6dB - 26 - [AK5366 ] 0dBFS -0.5dBFS -6dBFS -12dBFS 0dBFS -0.5dBFS -6dBFS -12dBFS 2004/05 ...

Page 27

... ALC OFF (WR: ALC = “0”) Manual Mode Set (SEL2-0 bits or SEL2-0 pins) WR (ZTM1-0, WTM1-0, LTM1-0) WR (LMAT, RATT, LMTH) WR (REF7-0) WR (IPGA7-0) (1) WR (ALC = “1”) (2) ALC Operation No Finish ALC mode? (1) Yes WR (ALC = “0”) (2) Finish ALC mode and return to manual mode Note : WR : Write - 27 - [AK5366 ] 2004/05 ...

Page 28

... The output signal is attenuated by −∞ within 1028 LRCK cycles (1028/fs). (2) Digital output delay from the analog input is called the group delay (GD). (3) If the soft mute is cancelled before the mute, the attenuation is discontinued and returned to DATT value. MS0309-E-00 ( (2) Figure 14. Soft Mute Function - 28 - [AK5366 ] ( 2004/05 ...

Page 29

... Control Data MS0309-E-00 2 C-bus control mode. C1 bit C0 bit L 0 Fixed to “1” Fixed to “1” 2 Table 12. Chip address in I C-bus control Figure 15. Serial Control I/F Timing - 29 - [AK5366 ] 2004/05 ...

Page 30

... HIGH defines a STOP condition (Figure 22). The AK5366 can perform more than one byte write operation per sequence. After receipt of the third byte the AK5366 generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the write cycle after the first data byte is transferred ...

Page 31

... ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK5366. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. ...

Page 32

... MASTER S START CONDITION SDA SCL MS0309-E-00 Figure 22. START and STOP Conditions Figure 23. Acknowledge on the I C-Bus data line change stable; of data data valid allowed 2 Figure 24. Bit Transfer on the I C-Bus - 32 - [AK5366 ] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2004/05 ...

Page 33

... Normal operation “H” : Soft muted Note : The SEL2-0 pins should be fixed to “LLL” if the AK5366 is controlled by the SEL2-0 bits, because the setting of the SEL2-0 pins are prior to the SEL2-0 bits setting. Soft Mute is ORed between pin and register. ...

Page 34

... When MCLK and LRCK are changed not necessary to reset by the PDN pin or PWN bit because the AK5366 builds in reset-free circuit. However, it can be reduced the noise by reset. MCKAC: Master Clock input Mode Select ...

Page 35

... ALC recovery operation waiting period 288/fs 1152/fs 2304/fs 4608/fs Table 14. ALC recovery waiting time Zero crossing timeout period 288/fs 1152/fs 2304/fs 4608/fs Table 15. Zero crossing timeout ALC limiter operation period 3/fs 6/fs 12/fs 24/fs Table 16. ALC limiter period - 35 - [AK5366 ] ZTM1 ZTM0 WTM1 WTM0 R/W R/W R/W R @fs=48kHz 6ms ...

Page 36

... MS0309-E- IPGL7 IPGL6 IPGL5 IPGL4 IPGR7 IPGR6 IPGR5 IPGR4 R/W R/W R/W R Step width (dB) 0.5 : 0.5 0.5 : 0.5 0.5 0.5 Analog volume with 0.5dB step 0.5 : 0.5 0.5 0 Table 17. IPGA Code Table - 36 - [AK5366 ] IPGL3 IPGL2 IPGL1 IPGL0 IPGR3 IPGR2 IPGR1 IPGR0 R/W R/W R/W R IPGA 2004/05 ...

Page 37

... Table 18. ALC limiter ATT step RATT Gain Step 0 1 Default 1 2 Table 19. ALC recovery gain step ALC Recovery Waiting Counter Reset Level −0.5dBFS > ALC Output ≥ −2.5dBFS −2.0dBFS > ALC Output ≥ −4.0dBFS - 37 - [AK5366 ] LMTH RATT LMAT R/W R/W R ...

Page 38

... PHL15-0: Lch Peak Hold Low/High Byte PHR15-0: Rch Peak Hold Low/High Byte The AK5366 includes the peak hold circuit. The peak is held L/R audio data independently. These registers are reset by reading 8bit of MSB, reading 8bit of both MSB and LSB should be continuity controlled by reading in order of 8bit of MSB from LSB. After reading 8bit of LSB the last, 8bit of MSB is lost by reading 8bit of LSB the last. The output value is the absolute value. Full scale is “ ...

Page 39

... Note: - AVSS and DVSS of the AK5366 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - When LOUT/ROUT drives a capacitive load, resistors should be added in series between LOUT/ROUT and capacitive load. - All digital input pins should not be left floating. ...

Page 40

... The ADC output data format 2’s compliment. The internal HPF removes the DC offset. The AK5366 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK5366 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. ...

Page 41

... ASAHI KASEI 44pin LQFP (Unit: mm) 12.80 ± 0.30 10. 0.37 ± 0.10 0.15 Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0309-E-00 PACKAGE 1.70max 0° 10° ~ 0.60 ± 0.20 Epoxy Cu Solder (Pb free) plate - 41 - [AK5366 ] 0 ~ 0.2 0.17 ± 0.05 2004/05 ...

Page 42

... ASAHI KASEI 1 XXXXXXX : Date (YY/MM/DD) Revision 04/05/25 00 MS0309-E-00 MARKING AKM AK5366VQ XXXXXXX Date Code Identifier (7 digits) Revision History Reason Page Contents First Edition - 42 - [AK5366 ] 2004/05 ...

Page 43

... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0309-E-00 IMPORTANT NOTICE - 43 - [AK5366 ] 2004/05 ...

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