ak5366vr AKM Semiconductor, Inc., ak5366vr Datasheet
ak5366vr
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ak5366vr Summary of contents
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... AK5366VR is a high-performance 24-bit, 48kHz sampling ADC for consumer audio and digital recording applications. Thanks to AKM’s Enhanced Dual-Bit modulator architecture, this analog-to-digital converter has an impressive dynamic range of 103dB with a high level of integration. The AK5366VR has a 5-channel stereo input selector, an input Programmable Gain Amplifier with an ALC function. All this integration with high-performance makes the AK5366VR well suited for CD and DVD recording systems ...
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... RIN2 Pre-Amp RIN3 RIN4 RIN5 ROPIN ROUT MS0526-E-00 M/S SEL2 SEL1 SEL0 IPGAL IPGA (ALC) ADC IPGA (ALC) IPGAR SMUTE Block diagram - 2 - [AK5366VR] PDN I2C HPF DATT Audio I/F Controller Peak Hold Control Register I/F CSN CCLK CDTI CAD1 SCL SDA 2006/07 AVDD AVSS ...
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... TEST2 4 LIN3 5 TEST3 6 LIN2 7 TEST4 8 LIN1 LOPIN 11 LOUT 12 13 MS0526-E-00 40 +85 C 48pin LQFP (0.5mm pitch) Evaluation Board for AK5366VR AK5366VR 31 30 Top View [AK5366VR ] CSN/CAD1 CCLK/SCL SDTI/SDA SEL2 ...
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... ATTL5 ATTL7 ATTR6 ATTR5 ATTR4 PHL7 PHL6 PHL5 PHL4 PHL15 PHL14 PHL13 PHL12 PHR7 PHR6 PHR5 PHR4 PHR15 PHR14 PHR13 PHR12 - 4 - [AK5366VR ] AK5366VR +18dB +8dB 48pin LQFP MCKPD MCKAC PWN 0 SEL2 SEL1 SEL0 DIF CKS1 CKS0 SMUTE ZTM1 ZTM0 ...
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... Digital Ground Pin 23 DVDD - Digital Power Supply Pin, 3.0 24 SDTO O Audio Serial Data Output Pin Note: All digital input pins except pull-down pins should not be left floating. Note: TEST1, TEST2, TEST3 and TEST4 pins should be connected to AVSS. MS0526-E-00 PIN/FUNCTION Function 5.25V 5.25V - 5 - [AK5366VR ] 2006/07 ...
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... C Control 2 C Control 2 C Control 2 C Control , “L” : 3-wire Control “L” : Slave Mode - 6 - [AK5366VR ] (I2C pin = “L”) (I2C pin = “H”) (I2C pin = “L”) (I2C pin = “H”) (I2C pin = “L”) (I2C pin = “H”) 2006/07 ...
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... IPGAR LOPIN/LOUT ROPIN/ROUT SMUTE SEL2-0 CSN Digital CCLK/SCL CDTI/SDA I2C MS0526-E-00 Setting These pins should be open. Connected 10k resistor between LOPIN pin and LOUT pin. Connected 10k resistor between ROPIN pin and ROUT pin. These pins should be connected to DVSS [AK5366VR ] 2006/07 ...
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... WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet. MS0526-E-00 ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD (Note 2) TVDD (Note 3) GND IIN (Note 4) VINA VIND1 VIND2 Ta Tstg Symbol min AVDD 4.75 DVDD 3.0 TVDD DVDD - 8 - [AK5366VR ] min max Units 0.3 6.0 V 0.3 6.0 V 0 0.3 AVDD+0.3 V 0.3 DVDD+0.3 V 0.3 TVDD+0 ...
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... Note 13. All digital input pins are held DVSS. MS0526-E-00 ANALOG CHARACTERISTICS 20kHz at fs=48kHz; unless otherwise specified) min 10 (Note 6) - (Note 6) - (Note 7) 6.3 (Note 8) 0.9 (Note 9) 6.3 0.2 0 9.5 (Note 10 (Note 11) 90 (Note 12) (Note 13) IPGA (Gain : 0dB [AK5366VR ] typ max Units 50 k 100 dB 108 1.1 Vrms 0.5 0.8 dB + Bits 94 ...
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... SB 26 CHARACTERISTICS 5.25V) Symbol min (Note 16) VIH 70%DVDD (Note 16) VIL - (Note 17) VAC 50%DVDD VOH DVDD 0.5 VOL - VOL - (Note 18) Iin - - 10 - [AK5366VR ] typ max Units 21.5 kHz 21.768 - kHz 22.0 - kHz 24.0 - kHz kHz 0.005 1/ 1.0 Hz 2.9 Hz 6.5 Hz typ max Units - ...
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... S mode) tLRS tBSD fBCK dBCK tMBLR 20 tBSD [AK5366VR ] typ max Units 24.576 MHz kHz 64fs ...
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... CSN “ ” to SDTO valid Note 21. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 22. The AK5366VR can be reset by bringing the PDN pin = “L”. Note 23. This cycle is the number of LRCK rising edges from the PDN pin = “H”. ...
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... LRCK BICK tBCKH 1000pF MCLK Input MCLK AC Coupling Timing (Measurement condition) *Refer to Figure 2 for input circuit example. MS0526-E-00 1/fCLK tCLKL 1/fs tBCK tBCKL Clock Timing Measurement Point 100k AGND AGND - 13 - [AK5366VR ] VIH VIL VIH VIL VIH VIL 1/fCLK tACW tACW VAC 2006/07 ...
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... CDTI MS0526-E-00 tLRB tBSD Audio Interface Timing (Slave mode) dBCK tBSD Audio Interface Timing (Master mode) tCSS tCCKL tCCKH tCDS C1 C0 WRITE Command Input Timing - 14 - [AK5366VR ] VIH VIL VIH VIL 50%DVDD 50%DVDD 50%DVDD 50%DVDD VIH VIL VIH VIL tCDH VIH R/W VIL ...
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... Start Bus Mode Timing tPDV tPDV tPD Power Down & Reset Timing - 15 - [AK5366VR ] tCSW VIH VIL VIH VIL VIH VIL tSP tSU:STO Stop VIH VIL ...
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... AK5366VR may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK5366VR in power-down mode (PDN pin = “L” or PWN bit = “0”). In master mode, the master clock (MCLK) must be provided unless PDN pin = “L”. ...
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... MCKPD = "0" AK5366VR 50%DVDD, Input circuit example) SDTO LRCK BICK 48fs (Slave) H/L 64fs (Master) 48fs (Slave Compatible L/H 64fs (Master) Table 4. Audio Interface Format - 17 - [AK5366VR ] MCKAC bit MCKPD bit Don’t care Figure Figure 3 Default Figure 4 2006/07 ...
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... T Master Mode and Slave Mode The M/S pin selects either master or slave mode. M/S pin = “H” selects master mode and “L” selects slave mode. The AK5366VR outputs BICK and LRCK in master mode. In slave mode, MCLK, BICK and LRCK are input externally. T Digital High Pass Filter The ADC has a digital high pass filter for DC offset cancellation ...
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... ASAHI KASEI T Power-up/down The AK5366VR is placed in the power-down mode by bringing PDN pin = “L” and the digital filter is also reset at the same time. This reset should always be done after power-up. An analog initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after 516 cycles of LRCK. ...
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... The AK5366VR includes 5ch stereo input selectors (Figure 6). The input selector selector. The input channel is set by the SEL2-0 bits (Table 6) and the SEL2-0 pins (Table 7). The SEL2-0 pins should be fixed to “LLL” if the AK5366VR is controlled by the SEL 2-0 bits, because the setting of the SEL2-0 pins are prior to the SEL2-0 bits setting. SEL2 bit ...
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... The period of (1) varies in the setting value of DATT. It takes 1028/fs to mute when DATT value is +8dB. When changing channels, the input channel should be changed during (2). The period of (2) should be around 200ms because there is some DC difference between the channels. MS0526-E-00 (1) (2) LIN 1 LIN 2 [AK5366VR ] (1) 2006/07 ...
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... MS0526-E-00 Rf LOPIN LOUT LIN1 LIN2 LIN3 LIN4 Pre-Amp LIN5 RIN1 RIN2 Pre-Amp RIN3 RIN4 RIN5 ROPIN ROUT Rf Figure 8. Input ATT ATT Gain [dB 11. Table 8. Input ATT example - 22 - [AK5366VR ] IPGAL To IPGA To IPGA IPGAR IPGAL/R pin 1.02Vrms 1.02Vrms 1Vrms 2006/07 ...
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... ASAHI KASEI T Input Volume The AK5366VR includes two independent channel analog volumes (IPGA) with 37 levels at 0.5dB steps located in front of the ADC. The IPGA is a true analog volume control that improves the S/N ratio as seen in Table 9. Independent zero-crossing detection is used to ensure level changes only occur during zero-crossings. If there are no zero-crossings, the level will then change after a time-out period (Table 10) ...
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... ALC operation. [2] ALC Recovery Operation The ALC recovery refers to the amount of time that the AK5366VR will allow a signal to exceed a predetermined limiting value prior to enabling the limiting function. The ALC recovery operation uses the WTM1-0 bits to define the wait period used after completing an ALC limiter operation. If the input signal does not exceed the “ ...
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... Figure 9. ALC Level diagram example (ALC=OFF) In Figure 10, Input ATT is 6dB. Input 2Vrms 1Vrms 0.5Vrms Figure 10. ALC Level diagram example (ALC=OFF) MS0526-E-00 ATT IPGA ADC -12dB -12dB +6dB +12dB ATT IPGA ADC -6dB -6dB -6dB +6dB -6dB +12dB - 25 - [AK5366VR ] 0dBFS 0dBFS 2006/07 ...
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... Figure 12. ALC Level diagram example (ALC=ON, LMTH=“0”) MS0526-E-00 ATT ALC ADC -12dB -12dB -0.5dB +5.5dB -12dB +6dB ATT ALC ADC -6dB -6dB -0.5dB -6dB +5.5dB -6dB +6dB - 26 - [AK5366VR ] 0dBFS -0.5dBFS -6dBFS -12dBFS 0dBFS -0.5dBFS -6dBFS -12dBFS 2006/07 ...
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... ALC OFF (WR: ALC = “0”) Manual Mode Set (SEL2-0 bits or SEL2-0 pins) WR (ZTM1-0, WTM1-0, LTM1-0) WR (LMAT, RATT, LMTH) WR (REF7-0) WR (IPGA7-0) (1) WR (ALC = “1”) (2) ALC Operation No Finish ALC mode? (1) Yes WR (ALC = “0”) (2) Finish ALC mode and return to manual mode Note : WR : Write - 27 - [AK5366VR ] 2006/07 ...
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... Digital output delay from the analog input is called the group delay (GD). (3) If the soft mute is cancelled before the mute, the attenuation is discontinued and returned to DATT value. MS0526-E-00 ( (2) Figure 14. Soft Mute Function within 1028 LRCK cycles (1028/fs [AK5366VR ] within 1028 ( 2006/07 ...
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... Figure 15. Serial Control I/F Timing - 29 - [AK5366VR ] ...
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... A “0” indicates that the write operation executed. The second byte consists of the control register address of the AK5366VR. The format is MSB first, and those most significant 3-bits are fixed to zeros (Figure 18). The data after the second byte contains control data. The format is MSB first, 8bits (Figure 19) ...
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... ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK5366VR. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle after the receipt of the first data word. ...
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... MASTER S START CONDITION SDA SCL MS0526-E-00 Figure 22. START and STOP Conditions Figure 23. Acknowledge on the I C-Bus data line change stable; of data data valid allowed 2 Figure 24. Bit Transfer on the I C-Bus - 32 - [AK5366VR ] P stop condition not acknowledge acknowledge 8 9 clock pulse for acknowledgement 2006/07 ...
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... Normal operation “H” : Soft muted Note : The SEL2-0 pins should be fixed to “LLL” if the AK5366VR is controlled by the SEL2-0 bits, because the setting of the SEL2-0 pins are prior to the SEL2-0 bits setting. Soft Mute is ORed between pin and register. ...
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... When MCLK and LRCK are changed not necessary to reset by the PDN pin or PWN bit because the AK5366VR builds in reset-free circuit. However, it can be reduced the noise by reset. MCKAC: Master Clock input Mode Select ...
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... Table 14. ALC recovery waiting time Zero crossing timeout period 288/fs 1152/fs 2304/fs 4608/fs Table 15. Zero crossing timeout ALC limiter operation period @fs=48kHz 3/fs 6/fs 12/fs 24/fs Table 16. ALC limiter period - 35 - [AK5366VR ] ZTM1 ZTM0 WTM1 WTM0 R/W R/W R/W R @fs=48kHz 6ms ...
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... MS0526-E- IPGL6 IPGL5 IPGL4 IPGR6 IPGR5 IPGR4 R/W R/W R/W R Step width (dB) 0.5 : 0.5 0.5 : 0.5 0.5 0.5 Analog volume with 0.5dB step 0.5 : 0.5 0.5 0 Table 17. IPGA Code Table - 36 - [AK5366VR ] IPGL3 IPGL2 IPGL1 IPGL0 IPGR3 IPGR2 IPGR1 IPGR0 R/W R/W R/W R IPGA 2006/07 ...
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... Table 18. ALC limiter ATT step RATT Gain Step 0 1 Default 1 2 Table 19. ALC recovery gain step ALC Recovery Waiting Counter Reset Level 0.5dBFS 0.5dBFS ALC Output 2.0dBFS 2.0dBFS ALC Output - 37 - [AK5366VR ] LMTH RATT LMAT R/W R/W R Default 2.5dBFS 4.0dBFS ...
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... PHL15-0: Lch Peak Hold Low/High Byte PHR15-0: Rch Peak Hold Low/High Byte The AK5366VR includes the peak hold circuit. The peak is held L/R audio data independently. These registers are reset by reading 8bit of MSB, reading 8bit of both MSB and LSB should be continuity controlled by reading in order of 8bit of MSB from LSB. After reading 8bit of LSB the last, 8bit of MSB is lost by reading 8bit of LSB the last. The output value is the absolute value. Full scale is “ ...
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... Note: - AVSS and DVSS of the AK5366VR should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - When LOUT/ROUT drives a capacitive load, resistors should be added in series between LOUT/ROUT and capacitive load. - All digital input pins should not be left floating. ...
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... The ADC output data format 2’s compliment. The internal HPF removes the DC offset. The AK5366VR samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of 64fs. The AK5366VR includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs. ...
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... ASAHI KASEI 48pin LQFP(Unit:mm) 9.0 7 0.5 0.22 0.10 T Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0526-E-00 PACKAGE 0 0.08 0. 0.5 0.2 Epoxy Cu Solder (Pb free) plate - 41 - [AK5366VR ] 1.70Max 0.13 0.13 1.40 0.05 0.16 0.07 2006/07 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0526-E-00 MARKING AK5366VR XXXXXXX Date Code Identifier (7 digits) Page Contents IMPORTANT NOTICE - 42 - [AK5366VR ] 2006/07 ...