xr16m2751 Exar Corporation, xr16m2751 Datasheet
xr16m2751
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xr16m2751 Summary of contents
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... Covered by U.S. Patent #5,649,122 and #5,949,787 APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls F 1. XR16M2751 B D IGURE LOCK IAGRAM PwrSave A2:A0 D7:D0 IOR# (VCC) IOW# (R/W#) CSA# (CS#) CSB# (A3) INTA (IRQ#) ...
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... TXA 7 TXB 8 OP2B PWRSAVE O T ACKAGE PERATING EMPERATURE -40°C to +85°C 2 REV. 1.0.0 RESET DTRB# DTRA RTSA# OP2A# 32 XR16M2751 31 RXRDYA# 48-pin TQFP IRQ (Motorola) Mode CLKSEL GND ANGE EVICE TATUS Active ...
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... INTA is set to the three state mode and OP2A logic 1 when MCR[3] is set to a logic 0. See MCR[3]. When 16/68# pin is LOW for Motorola bus interface, this output becomes device interrupt output (active low, open drain). An external pull-up resistor is required for proper operation. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO D ESCRIPTION 3 XR16M2751 ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Pin Description 48-TQFP N T AME YPE INTB 29 O UART channel B Interrupt output. The output state is defined by the user through the software setting of MCR[3]. INTB is set to the active mode and OP2B# output LOW when MCR[3] is set to a logic 1 ...
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... PowerSave (active high). This feature isolates the 2751’s data bus interface from the host preventing other bus activities that cause higher power drain during sleep mode. See Sleep Mode with Auto Wake-up and PowerSave Feature section for details. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO D ESCRIPTION 5 XR16M2751 ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Pin Description 48-TQFP N T AME YPE 16/68 Intel or Motorola Bus Select. When 16/68# pin is HIGH Intel Mode, the device will operate in the Intel bus type of interface. When 16/68# pin is LOW Motorola mode, the device will operate in the Motor- ola bus type of interface ...
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... Xoff and special character software flow control, programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide The XR16M2751 can operate from 1.62V to 3.63V. The M2751 is fabricated with an advanced CMOS process. ...
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... Each bus cycle is asynchronous using CSA/B#, IOR# and IOW# or CS#, R/W# and A3 inputs. Both UART channels share the same data bus for host operations. A typical data bus interconnection for Intel and Motorola mode is shown in Figure F 3. XR16M2751 T I IGURE YPICAL NTEL ...
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... To read the identification code from the part required to set the baud rate generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DLM will provide 0x0A for the XR16M2751 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means revision A. ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive FIFO in the DMA mode (FCR bit-3=1) ...
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... Also, when using 8X sampling mode, please note that the bit- 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 4. T YPICAL OSCILLATOR CONNECTIONS XTAL1 XTAL2 R1 0-120 Ω (Optional) R2 500 ΚΩ − 1 ΜΩ 1.8432 MHz MHz C1 C2 22-47 pF 22- XR16M2751 11.” Figure 4). The programmable Baud Table 6. At ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a non- standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s): Required Divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16), with 16X mode EMSR[ ...
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... XR16M2751 16X S AMPLING DLD ROGRAM ROGRAM ATA RROR (HEX) V (HEX) R (%) ALUE ATE ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.10.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits, parity-bit and stop-bit(s) ...
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... ODE ive hift D ata giste alid a tio ive Inte rru ldin ister ( XR16M2751 ive cte ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IGURE ECEIVER PERATION IN 16X or 8X Clock (EMSR bit-7) Receive Data Shift Register (RSR) 64 bytes by 11-bit wide FIFO Data FIFO Receive Data Byte and Errors N : Table-B selected as Trigger Table for OTE 2 ...
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... RXA TXB RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend 9 RTS High RTS Low 5 Threshold Threshold 17 XR16M2751 Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.15 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled data characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M2751 will halt transmission (TX) as soon as the current character has completed transmission ...
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... Figure 11 below. Figure 11 RANSMIT ATA NCODING AND Character Data Bits Bit Time 3/16 Bit Time Bit Time 1/16 Clock Delay Data Bits Character 19 XR16M2751 ECEIVE ATA ECODING 1 1/2 Bit Time IrEncoder IRdecoder- ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.19 Sleep Mode with Wake-Up Indicator and PowerSave Feature The M2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave feature is included to reduce power consumption when the device is not actively used. ...
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... TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ACK IN HANNEL AND VCC (THR/FIFO) MCR bit-4=1 (RHR/FIFO) VCC RTS# CTS# VCC DTR# DSR# OP1# RI# VCC OP2# CD# 21 XR16M2751 TXA/TXB RXA/RXB RTSA#/RTSB# CTSA#/CTSB# DTRA#/DTRB# DSRA#/DSRB# RIA#/RIB# OP2A#/OP2B# CDA#/CDB# ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 3.0 UART INTERNAL REGISTERS Each of the UART channel in the M2751 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or CSB# selecting the channel. The complete register set is shown on Table 9 ...
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... Bit-4 Bit-3 LSR Auto Auto Auto Error RS485 RTS RTS Inter- Output Hyst. Hyst. rupt. Inversion bit-3 bit-2 Imd/Dly# Bit-6 Bit-5 Bit-4 Bit-3 23 XR16M2751 EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 Bit-2 Bit-1 Bit-0 RX Line TX RX LCR[7]=0 Stat ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ABLE NTERNAL EGISTERS DDRESS EG EAD A2- AME RITE DLL RD/WR Bit DLM RD/WR Bit DLD RD/ DREV RD Bit DVID TRG WR Bit ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M2751 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IER[4]: Sleep Mode Enable (requires EFR bit • Logic 0 = Disable Sleep Mode (default). • Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details. IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • ...
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... LSR (Receiver Line Status Register RXRDY (Receive Data Time-out RXRDY (Received Data Ready TXRDY (Transmit Ready MSR (Modem Status Register RXRDY (Received Xoff or Special character CTS#, RTS# change of state None (default) or Wake-up Indicator 27 XR16M2751 L EVEL S OURCE OF INTERRUPT ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ISR[7:6]: FIFO Enable Status These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are enabled. 4.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and select the DMA mode ...
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... Programmable via TRG register. FCTR[ BIT-0 W ORD LENGTH 0 5 (default XR16M2751 L S EVEL ELECTION T RANSMIT T C RIGGER OMPATIBILITY L EVEL 1 (default) 16C550, 16C2550, 16C2552, 16C554, 16C580 16 16C650A 16C654 Programmable 16L2752, 16C2850, ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check ...
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... Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation. The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and the M2751 is programmed to use the Xon/Xoff flow control. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Figure 31 XR16M2751 12. ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO MCR[6]: Infrared Encoder/Decoder Enable • Logic 0 = Enable the standard modem receive and transmit input/output interface (default). • Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface requirement ...
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... Normally this bit is the complement of the DSR# input. In the loopback mode, this bit is equivalent to the DTR# bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is not used. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 33 XR16M2751 ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO MSR[6]: RI Input Status Normally this bit is the complement of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the MCR register. The RI# input may be used as a general purpose input when the modem interface is not used. ...
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... EFR bit-4 before it can be accessed. FRACTIONAL DIVISOR” ON PAGE 11. 4.14 Device Identification Register (DVID) - Read Only This register contains the device ID (0x0A for XR16M2751). Prior to reading this register, DLL and DLM should be set to 0x00 (DLD = 0xXX). 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T ...
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... Feature Control Register (FCTR) - Read/Write This register controls the XR16M2751 new functions that are not available in ST16C2450 or ST16C2550. FCTR[1:0]: RTS Hysteresis User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to “0” to select the next trigger level for hardware flow control. See FCTR[2]: IrDa RX Inversion • ...
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... flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T 15 ABLE RIGGER ABLE ELECT FCTR T ABLE Table-A (TX/RX) 1 Table-B (TX/RX) 0 Table-C (TX/RX) 1 Table-D (TX/RX) Table 16). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes 37 XR16M2751 ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. T ABLE EFR -3 EFR -2 BIT BIT EFR ONT ...
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... Data transmission resumes when CTS# returns LOW. 4.19.1 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. For more details, see Table 7. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 39 XR16M2751 ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T 17: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They do not reset when the Reset Pin is asserted. DLD Bits 7-0 = 0x00 ...
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... -0.3 0.3 -0.3 0.4 -0.3 1.4 VCC 2.0 VCC -0.3 0.2 -0.3 0.5 -0.3 1.4 VCC 1.8 VCC 0.4 0.4 1.8 1.4 ±10 ±10 ±10 ± 1 XR16M2751 7 Volts GND-0. - -65 to +150 C 500 C/W, theta- C/W 1.62V 3.63V TO L IMITS 3. NITS ONDITIONS 0.6 V 2.4 VCC V 0.7 V 2.0 VCC V 0 ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO For PowerSave, the UART internally isolates all of these inputs (except the modem inputs) therefore eliminating any unnecessary external buffers to keep the inputs steady. PAGE 20. AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED 3.63V, 70 ...
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... C (-40 + FOR INDUSTRIAL GRADE PACKAGE L IMITS 1.8V ± 10 16X data rate T ECLK T ECH 43 XR16M2751 ), V =1. IMITS IMITS 2.5V ± 10% 3.3V ± 10% U NIT Bclk ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 14 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI IGURE ODE NTEL ATA A0-A2 Valid Address T AS CSA#/ CSB# IOR# T RDV D0- & B ...
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... RITE IMING Valid Data ATA US EAD IMING T T CSL ADH T CSD T RWH T RDH Valid Data 45 XR16M2751 Valid Address Valid Data 16Write Valid Address Valid Data 68Read ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 18 IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# T RWS R/W# D0- & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR ATA US RITE IMING T T CSL ...
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... T WRI T SRT [FIFO M , DMA D IMING ODE ISABLED D0:D7 D0:D7 D0: SSI RX FIFO fills Trigger Level or RX Data Timeout 47 XR16M2751 C A & B HANNELS D0:D7 ISR is read T WRI T SRT T WT TXNonFIFO ] C A & B FOR HANNELS D0:D7 D0: FIFO drops below RX Trigger Level ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 22 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX D0:D7 D0: INT RX FIFO fills Trigger Level or RX Data Timeout RXRDY# IOR# (Reading data out of RX FIFO & I IGURE ...
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... TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T [FIFO M , DMA M IMING ODE D0:D7 S D0:D7 S D0: SRT TX FIFO fills up to trigger level T WRI TX FIFO Full 49 XR16M2751 & B ODE NABLED FOR HANNELS Last Data Byte Transmitted S D0: D0: ISR Read FIFO drops ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL INCHES ...
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... Copyright 2007 EXAR Corporation Datasheet August 2007. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO D ESCRIPTION NOTICE 51 XR16M2751 ...
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... REV. 1.0.0 GENERAL DESCRIPTION................................................................................................ 1 A .............................................................................................................................................. 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR16M2751 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT O .............................................................................................................................. 2 RDERING INFORMATION PIN DESCRIPTIONS ........................................................................................................ 3 1.0 PRODUCT DESCRIPTION ...................................................................................................................... 7 2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 8 2.1 CPU INTERFACE ................................................................................................................................................ XR16M2751 T I IGURE YPICAL NTEL 2.2 DEVICE RESET ................................................................................................................................................... 8 2.3 DEVICE IDENTIFICATION AND REVISION ....................................................................................................... 9 2 ...
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... XR16M2751 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 25 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 25 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 26 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 26 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... 28 ...