xr16m2752 Exar Corporation, xr16m2752 Datasheet
xr16m2752
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xr16m2752 Summary of contents
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... Covered by U.S. Patent #5,649,122 OTE APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls F 1. XR16M2752 B D IGURE LOCK IAGRAM A2:A0 D7:D0 IOR# IOW# CS# CHSEL INTA INTB 8-bit Data TXRDYA# ...
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... XTAL1 XTAL2 CHSEL ORDERING INFORMATION ART UMBER XR16M2752IL32 XR16M2752IJ44 44-Lead PLCC XR16M2752 44-pin PLCC XR16M2752 21 4 32-pin QFN CTSB ACKAGE PERATING EMPERATURE 32-QFN -40°C to +85°C -40°C to +85°C 2 REV. 1.0.0 ...
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... MCR[ this mode, the TX signal will be HIGH during reset or idle (no data). Infrared IrDA transmit and receive interface is enabled when MCR[ the Infrared mode, the inactive state (no data) for the Infrared encoder/decoder interface is LOW not used, leave it unconnected. 3 XR16M2752 ESCRIPTION Figures ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Pin Description 32-QFN 44-PLCC N AME RXA 24 39 RTSA CTSA DTRA DSRA CDA RIA MFA TXB 16 26 RXB YPE I UART channel A Receive Data or infrared receive data. Normal receive data input must idle HIGH ...
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... GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be sol- der mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad Connect. 5 XR16M2752 ESCRIPTION ...
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... FIFO trigger levels, FIFO level counters, infrared encoder and decoder (IrDA ver 1.0), programmable fractional baud rate generator with a prescaler of divide and data rate Mbps with 8X sampling clock rate or 4 Mbps in the 16X rate. The XR16M2752 is a 1.62 to 3.63V device. The M2752 is fabricated with an advanced CMOS process. ...
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... To read the identification code from the part required to set the baud rate generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DLM will provide 0x0A for the XR16M2752 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means revision A. ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO CS 2.5 Channel A and B Internal Registers Each UART channel in the M2752 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard single 16C550 and dual ST16C2550 ...
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... LOW = FIFO below trigger level HIGH = FIFO above trigger level 4. T YPICAL OSCILLATOR CONNECTIONS XTAL1 XTAL2 R1 0-120 Ω (Optional) R2 500 ΚΩ − 1 ΜΩ 1.8432 MHz MHz C1 C2 22-47 pF 22- XR16M2752 Figures 17 T RANSMITTER - (FIFO NABLED R ECEIVER FCR NABLED 10.” ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins (see Rate Generator is capable of operating with a crystal oscillator frequency MHz ...
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... XR16M2752 16X or 8X Sampling Rate Clock to Transmitter and Receiver 16X S AMPLING DLD ROGRAM ROGRAM ATA RROR (HEX) V (HEX) R (%) ALUE ATE ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.10 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 64 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X internal clock. A bit time is 16 (8) clock periods (see EMSR bit-7). The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s) ...
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... TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO FIFO AND LOW ONTROL ODE Transm it THR Interrupt (ISR bit-1) falls FIFO below the programmed Trigger Level and then when becomes empty. FIFO is Enabled by FCR bit-0=1 Transm it Data Shift Register (TSR) 13 XR16M2752 ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO IGURE ECEIVER PERATION IN NON it rro r R ece ive yte its rro IGURE ...
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... CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re- asserted (LOW), indicating more data may be sent. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Figure 10): Table 13 10): 15 XR16M2752 shows the complete details for the ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 10. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts 4 RXA FIFO ...
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... M2752 compares one or two sequential receive Table 6 below explains this when Trigger Table-B (See UTO ON OFF OFTWARE LOW OFF HARACTER S ENT ( ) CHARACTERS IN RX FIFO 8* 16* 24* 28* 17 XR16M2752 Table 10 ONTROL HARACTER S ENT ( ) CHARACTERS IN RX FIFO ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.18 Infrared Mode The M2752 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/ bit wide HIGH-pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See The infrared encoder and decoder are enabled by setting MCR register bit ‘ ...
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... This may occur when the external interface transceivers (RS-232, RS-485 or another type) are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a 47k-100k ohm pull-up resistor on the RXA and RXB pins. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 19 XR16M2752 ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 2.20 Internal Loopback The M2752 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 12 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...
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... Read-only Write-only E R NHANCED EGISTERS Write-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 21 XR16M2752 Table EAD RITE OMMENTS LCR[ LCR[ LCR ≠ 0xBF LCR[ LCR ≠ 0xBF, EFR[ LCR[ LCR ≠ 0xBF, EFR[ DLL, DLM = 0x00, LCR[ LCR ≠ 0xBF LCR[ LCR ≠ ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO . ABLE NTERNAL EGISTERS DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/WR 0/ CTS Int. Enable ISR RD FIFOs Enabled FCR WR RX FIFO Trigger ...
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... Flow FCR[5:4], Cntl MCR[7:5], Bit-3 DLD Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 23 XR16M2752 EFR B -4 OMMENT LCR[7]=1 Bit-2 Bit-1 Bit-0 LCR ≠ 0xBF Bit-2 Bit-1 Bit-0 ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M2752 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received. • Special character interrupt is cleared by a read to ISR or after the next character is received. • RTS# and CTS# flow control interrupts are cleared by a read to the MSR register. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 25 XR16M2752 ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ] T ABLE P ISR R RIORITY EGISTER EVEL ISR[0]: Interrupt Status • Logic interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. • ...
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... Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO Table 10 below shows the selections. EFR bit-4 27 XR16M2752 ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO T 10: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table Table Table 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format ...
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... TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO S W TOP BIT LENGTH ORD (B LENGTH IT TIME 5,6,7,8 1 (default) 5 1-1/2 6,7 11: P ABLE ARITY SELECTION -4 LCR ARITY SELECTION parity 0 1 Odd parity 1 1 Even parity 0 1 Force parity to mark, “1” Forced parity to space, “0” 29 XR16M2752 ( )) S ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space", LOW state). This condition remains, until disabled by setting LCR bit logic 0. ...
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... In the FIFO mode this bit is set when the transmit FIFO is empty cleared when the transmit FIFO contains at least 1 byte. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 31 XR16M2752 SEE”INFRARED MODE” ON ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO LSR[6]: THR and TSR Empty Flag This bit is set to a logic 1 whenever the transmitter goes idle set to logic 0 whenever either the THR or TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and transmit shift register are both empty ...
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... Logic 0 = RTS# output is LOW during TX and HIGH during RX (default, compatible with 16C2850). • Logic 1 = RTS# output is HIGH during TX and LOW during RX. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 12 ABLE CRATCHPAD WAP ELECTION X Scratchpad 0 RX FIFO Level Counter Mode 1 TX FIFO Level Counter Mode 1 Alternate RX/TX FIFO Counter Mode 33 XR16M2752 ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[6]: LSR Interrupt Mode • Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an interrupt when the character with the error is in the RHR. • ...
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... AFR[7:3]: Reserved All are initialized to logic 0. 4.14 Device Identification Register (DVID) - Read Only This register contains the device ID (0x0A for XR16M2752). Prior to reading this register, DLL and DLM should be set to 0x00 (DLD = 0xXX). 4.15 Device Revision Register (DREV) - Read Only This register contains the device revision information. For example, 0x01 means revision A. Prior to reading this register, DLL and DLM should be set to 0x00 (DLD = 0xXX) ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO FCTR[1:0]: RTS Hysteresis User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to “0” to select the next trigger level for hardware flow control. See FCTR[2]: IrDa RX Inversion • ...
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... Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 37 XR16M2752 ECEIVE OFTWARE LOW ONTROL ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and RTS de-asserts HIGH at the next upper trigger level or hysteresis level ...
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... XON1 Bits 7-0 = 0x00 XON2 Bits 7-0 = 0x00 XOFF1 Bits 7-0 = 0x00 XOFF2 Bits 7-0 = 0x00 FC Bits 7-0 = 0x00 I/O SIGNALS TX HIGH OP2# HIGH RTS# HIGH DTR# HIGH RXRDY# HIGH TXRDY# LOW INT LOW 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO RESET STATE RESET STATE 39 XR16M2752 ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (44-PLCC) Thermal Resistance (32-QFN) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS O O TA=-40 + ...
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... XR16M2752 F LOAD WHERE APPLICABLE L L IMITS IMITS 3.3V ± 10% U NIT MHz 50 64 MHz ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AC ELECTRICAL CHARACTERISTICS U : TA=-40 NLESS OTHERWISE NOTED S P YMBOL ARAMETER T Reset Pulse Width RST Bclk Baud Clock F 13 IGURE LOCK IMING VIH External Clock VIL F 14 IGURE ODEM NPUT UTPUT IOW # ...
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... TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO RDV Valid Data Valid Data 43 XR16M2752 Valid Address Valid Data RDTm Valid Address Valid Data 16Write ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 17 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT ...
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... SSI RX FIFO fills Trigger Level or RX Data Timeout T [FIFO M , DMA E IMING ODE NABLED D0:D7 D0:D7 D0: SSI T SSR 45 XR16M2752 ] C A & B FOR HANNELS S D0: D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXINTDMA & B FOR HANNELS ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO F 21 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO TXRDY IOW# (Loading data into FIFO) *INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level. ...
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... MIN 0.165 0.180 4.19 0.090 0.120 2.29 0.020 --- 0.51 0.013 0.021 0.33 0.026 0.032 0.66 0.008 0.013 0.19 0.685 0.695 17.40 0.650 0.656 16.51 0.590 0.630 14.99 0.500 typ. 12.70 typ. 0.050 BSC 1.27 BSC 0.042 0.056 1.07 0.042 0.048 1.07 0.025 0.045 0.64 47 XR16M2752 C Seating Plane MAX 4.57 3.05 --- 0.53 0.81 0.32 17.65 16.66 16.00 1.42 1.22 1.14 ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.193 0.201 4.90 0.138 ...
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... Copyright 2007 EXAR Corporation Datasheet August 2007. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO D ESCRIPTION NOTICE 49 XR16M2752 ...
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... REV. 1.0.0 GENERAL DESCRIPTION................................................................................................ 1 A .............................................................................................................................................. 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR16M2752 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT O .............................................................................................................................. 2 RDERING INFORMATION PIN DESCRIPTIONS ........................................................................................................ 3 1.0 PRODUCT DESCRIPTION ...................................................................................................................... 6 2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 7 2.1 CPU INTERFACE ................................................................................................................................................ XR16L2750 IGURE ATA US NTERCONNECTIONS 2.2 DEVICE RESET ................................................................................................................................................... 7 2.3 DEVICE IDENTIFICATION AND REVISION ....................................................................................................... 7 2 ...
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... XR16M2752 1.62V TO 3.63V HIGH PERFORMANCE DUART WITH 64-BYTE FIFO 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 25 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... FIFO T ABLE RANSMIT AND ECEIVE 4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE......................................................................................... 28 T 11: P ........................................................................................................................................................ 29 ABLE ARITY SELECTION 4 ...