xr16m2550 Exar Corporation, xr16m2550 Datasheet
xr16m2550
Available stocks
Related parts for xr16m2550
xr16m2550 Summary of contents
Page 1
... Covered by U.S. Patent #5,649,122 OTE APPLICATIONS • Portable Appliances • Telecommunication Network Routers • Ethernet Network Routers • Cellular Data Devices • Factory Automation and Process Controls F 1. XR16M2550 B D IGURE LOCK IAGRAM A2:A0 D7:D0 IOR# IOW# CSA# CSB# 8-bit Data INTA Bus ...
Page 2
... UMBER XR16M2550IL32 32-Pin QFN XR16M2550IM48 48-Lead TQFP XR16M2550 6 48-pin TQFP XR16M2550 21 4 32-pin QFN ACKAGE PERATING EMPERATURE -40°C to +85°C -40°C to +85°C 2 REV. 1.0.2 36 RESET 35 DTRB# DTRA# 34 ...
Page 3
... RX FIFO/RHR status for receive channel A. See used, leave it unconnected. O UART channel B Transmitter Ready (active low). The output provides the TX FIFO/THR status for transmit channel B. See used, leave it unconnected. 3 XR16M2550 ESCRIPTION Table not Table not Table not ...
Page 4
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO Pin Description 32-QFN 48-TQFP N AME RXRDYB MODEM OR SERIAL I/O INTERFACE TXA 5 7 RXA 4 5 RTSA CTSA DTRA DSRA CDA RIA OP2A TXB 6 8 RXB YPE ESCRIPTION O UART channel B Receiver Ready (active low). This output provides the RX FIFO/RHR status for receive channel B ...
Page 5
... GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad. No Connection. 5 XR16M2550 ESCRIPTION ...
Page 6
... CMOS process. Enhanced Features The XR16M2550 (M2550) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Each UART is independently controlled its own set of device configuration registers. The configuration registers set is 16550 UART compatible for control, status and data transfer. Additionally, each UART channel has automatic RTS/CTS hardware flow control, automatic Xon/Xoff and special character software flow control, infrared encoder and decoder (IrDA ver 1 ...
Page 7
... To read the identification code from the part required to set the baud rate generator registers DLL and DLM both to 0x00 (DLD = 0xXX). Now reading the content of the DVID will provide 0x02 for the XR16M2550 and reading the content of DREV will provide the revision of the part; for example, a reading of 0x01 means revision A. ...
Page 8
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO registers, but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in Table 1. CSA 2.5 Channel A and B Internal Registers Each UART channel in the M2550 has a set of enhanced registers for control, monitoring and data loading and unloading ...
Page 9
... LOW = FIFO below trigger level HIGH = FIFO above trigger level 4. T YPICAL OSCILLATOR CONNECTIONS XTAL1 XTAL2 R1 0-120 Ω (Optional) R2 500 ΚΩ − 1 ΜΩ 1.8432 MHz MHz C1 C2 22-47 pF 22- XR16M2550 Figures 17 RANSMITTER - (FIFO E ) NABLED R ECEIVER FCR NABLED 10.” ...
Page 10
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency tolerance) connected externally between the XTAL1 and XTAL2 pins (see Rate Generator is capable of operating with a crystal oscillator frequency MHz ...
Page 11
... XR16M2550 16X Sampling Rate Clock to Transmitter and Receiver 16X S AMPLING DLD ROGRAM ROGRAM ATA RROR (HEX) V (HEX) R (%) ALUE ATE ...
Page 12
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 2.10 Transmitter The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X/8X/4X internal clock. A bit time is 16/8/4 clock periods (see DLD). The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and adds the stop-bit(s) ...
Page 13
... HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO FIFO AND LOW ONTROL ODE Transmit Transmit THR Interrupt (ISR bit-1) falls FIFO below the programmed Trigger Level and then when becomes empty. FIFO is Enabled by FCR bit-0=1 Transmit Data Shift Register (TSR) Figure 8 and Figure 9 below. 13 XR16M2550 TXFIFO1 ...
Page 14
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO IGURE ECEIVER PERATION IN NON rro ive yte its rro ...
Page 15
... HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO Figure 10 RTS ( UTO ARDWARE LOW RTS ASSERTED A IN CTIVATION (C HARACTERS 10): 15 XR16M2550 ONTROL (H ) RTS IGH SSERTED IFO HARACTERS IN X IFO ...
Page 16
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO F 10. A RTS CTS F IGURE UTO AND LOW Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# 2 CTSB# 3 TXB Data Starts 4 RXA FIFO ...
Page 17
... HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO (See Table 14), the M2550 compares one or two sequential receive UTO ON OFF OFTWARE LOW OFF HARACTER S ENT ( ) CHARACTERS IN RX FIFO 14* 17 XR16M2550 C ONTROL HARACTER S ENT ( ) CHARACTERS IN RX FIFO ...
Page 18
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 2.17 Infrared Mode The M2550 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/ bit wide HIGH-pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the infrared LED, hence reduces the power consumption. See The infrared encoder and decoder are enabled by setting MCR register bit ‘ ...
Page 19
... This may occur when the external interface transceivers (RS-232, RS-422 or another type) are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a 47k-100k ohm pull-up resistor on the RXA and RXB pins. HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 19 XR16M2550 ...
Page 20
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 2.19 Internal Loopback The M2550 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 12 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...
Page 21
... Read/Write Read/Write Read-only Read-only Read/Write E R NHANCED EGISTERS Read/Write Read/Write Read/Write Read/Write Read/Write 21 XR16M2550 Table 8 and /W C RITE OMMENTS LCR[ LCR[ LCR ≠ 0xBF LCR[ LCR ≠ 0xBF, EFR[ DLL, DLM = 0x00, LCR[ LCR ≠ 0xBF LCR[ LCR ≠ 0xBF LCR ≠ 0xBF ...
Page 22
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO . T 9: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/WR 0/ CTS Int. Enable ISR RD FIFOs Enabled FCR WR RX FIFO Trigger ...
Page 23
... ISR [5:4], Flow FCR[5:4], Cntl MCR[7:5], Bit-3 DLD Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 23 XR16M2550 EFR B -4 OMMENT Soft- Soft- Soft- ware ware ware Flow Flow Flow ...
Page 24
... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M2550 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
Page 25
... Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received. • Special character interrupt is cleared by a read to ISR or after the next character is received. • RTS# and CTS# flow control interrupts are cleared by a read to the MSR register. HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 25 XR16M2550 ...
Page 26
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO ] T ABLE P ISR R RIORITY EGISTER EVEL ISR[0]: Interrupt Status • Logic interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt service routine. • ...
Page 27
... EFR bit-4 Table 11 R FIFO T L ECEIVE RIGGER EVEL T RANSMIT FCR R ECEIVE T RIGGER - BIT RIGGER EVEL L EVEL 0 1 (default (default XR16M2550 shows the complete selections. S ELECTION C OMPATIBILITY 16C550, 16C2550, 16C2552, 16C554, 16C580 compatible. ...
Page 28
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO LCR[1:0]: TX and RX Word Length Select These two bits specify the word length to be transmitted or received. BIT LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. ...
Page 29
... In the Internal Loopback Mode, this bit controls the state of the modem input RI# bit in the MSR register as shown in Figure 12. HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO T 12: P ABLE ARITY SELECTION LCR Force parity to mark, HIGH 1 Force parity to space, LOW 29 XR16M2550 P ARITY SELECTION No parity Odd parity Even parity ...
Page 30
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO MCR[3]: OP2# Output / INT Output Enable This bit enables or disables the operation of INT, interrupt output. If INT output is not used, OP2# can be used as a general purpose output. • Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set HIGH(default). ...
Page 31
... MSR[2]: Delta RI# Input Flag • Logic change on RI# input (default). • Logic 1 = The RI# input has changed from a LOW to HIGH, ending of the ringing signal. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 31 XR16M2550 ...
Page 32
... See DLD[ 4.12 Device Identification Register (DVID) - Read Only This register contains the device ID (0x02 for XR16M2550). Prior to reading this register, DLL and DLM should be set to 0x00 (DLD = 0xXX). Table 13 below and 10. T 13: S ...
Page 33
... Receiver compares Xon1 or Xon2, Xoff1 or Xoff2 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 transmit flow control, Receiver compares Xon1 and Xon2, Xoff1 and Xoff2 33 XR16M2550 ECEIVE OFTWARE LOW ONTROL ...
Page 34
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO EFR[5]: Special Character Detect Enable • Logic 0 = Special Character Detect Disabled (default). • Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with data in Xoff-2 register match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘ ...
Page 35
... Bits 7-0 = 0x00 XON1 Bits 7-0 = 0x00 XON2 Bits 7-0 = 0x00 XOFF1 Bits 7-0 = 0x00 XOFF2 Bits 7-0 = 0x00 I/O SIGNALS TX HIGH OP2# HIGH RTS# HIGH DTR# HIGH RXRDY# HIGH TXRDY# LOW INT Three-State Condition HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO RESET STATE RESET STATE 35 XR16M2550 ...
Page 36
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO 5.0 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA ( Thermal Resistance (48-TQFP) Thermal Resistance (32-QFN) DC ELECTRICAL CHARACTERISTICS o o TA=-40 to +85 C, Vcc is 1 ...
Page 37
... 16X data rate 37 XR16M2550 L L IMITS IMITS 2.5V ± 10% 3.3V ± 10% U NIT MHz 50 64 MHz ...
Page 38
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO F 13 IGURE LOCK IMING VIH External Clock VIL F 14 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI# T ECLK T ECH & B IMING ...
Page 39
... HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO RDV Valid Data Valid Data 39 XR16M2550 Valid Address Valid Data RDTm Valid Address Valid Data 16Write ...
Page 40
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO F 17 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT ...
Page 41
... SSI RX FIFO fills Trigger Level or RX Data Timeout T [FIFO M , DMA E IMING ODE NABLED D0:D7 D0:D7 D0: SSI T SSR 41 XR16M2550 ] C A & B FOR HANNELS D0:D7 D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXINTDMA & B FOR HANNELS ...
Page 42
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO F 21 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX D0:D7 S (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in TX FIFO TXRDY IOW# (Loading data into FIFO) *INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level. ...
Page 43
... INCHES MILLIMETERS MIN MAX MIN 0.039 0.047 1.00 0.002 0.006 0.05 0.037 0.041 0.95 0.007 0.011 0.17 0.004 0.008 0.09 0.346 0.362 8.80 0.272 0.280 6.90 0.020 BSC 0.50 BSC 0.018 0.030 0.45 0° 7° 0° 43 XR16M2550 α L MAX 1.20 0.15 1.05 0.27 0.20 9.20 7.10 0.75 7° ...
Page 44
... XR16M2550 HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO PACKAGE DIMENSIONS (32 PIN QFN - 0.9 mm) Note: The control dimension is in millimeter. SYMBOL INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.193 0.201 4.90 0.138 0.150 3 ...
Page 45
... Copyright 2007 EXAR Corporation Datasheet May 2007. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. HIGH PERFORMANCE LOW VOLTAGE DUART WITH 16-BYTE FIFO D ESCRIPTION NOTICE 45 XR16M2550 ...
Page 46
... LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT ................................................................................................................................ 2 ORDERING INFORMATION PIN DESCRIPTIONS ........................................................................................................ 3 1.0 PRODUCT DESCRIPTION....................................................................................................................... 6 2.0 FUNCTIONAL DESCRIPTIONS............................................................................................................... 7 2.1 CPU INTERFACE................................................................................................................................................. XR16M2550 IGURE ATA US NTERCONNECTIONS 2.2 DEVICE RESET ................................................................................................................................................... 7 2.3 DEVICE IDENTIFICATION AND REVISION........................................................................................................ 7 2.4 CHANNEL A AND B SELECTION....................................................................................................................... ............................................................................................................................................... 8 ABLE HANNEL AND ELECT 2 ...
Page 47
... DMA M D IMING ODE ODE ISABLED T [FIFO M , DMA M E IMING ODE ODE NABLED - .................................................................................. 0.9 ) ............................................................................... XR16M2550 A & B ......................................................... 40 A & B ....................................................... & B........................................ 41 HANNELS C A & B......................................... 41 HANNELS ] C A & B ........................... 42 FOR HANNELS ] C A & B ............................ 42 FOR HANNELS I ...