xr16m780 Exar Corporation, xr16m780 Datasheet
xr16m780
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xr16m780 Summary of contents
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... N : OTE 1 Covered by U.S. Patent #5,649,122 XR16M780 B D IGURE LOCK IAGRAM ave Intel or ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO IGURE IN UT SSIGNMENT DSR# 25 CD# 26 RI# 27 32- pin QFN in VCC 28 Intel Bus Mode VCC ...
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... Transparent Top View RESET INT A1 16/68# RTS PwrSave PERATING P ACKAGE 32-Pin QFN -40°C to +85°C 48-Lead TQFP -40°C to +85°C 25-Pin BGA -40°C to +85°C 3 XR16M780 A2 IOR# IOW# XTAL1 GND T EMPERATURE D S EVICE TATUS R ANGE Active Active Active ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO PIN DESCRIPTIONS Pin Description 32-QFN 48-TQFP 25-BGA N AME P # PIN DATA BUS INTERFACE IOR IOW# ...
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... GND on the PCB. The thermal pad size on the PCB should be the approximate size of this center pad and should be solder mask defined. The solder mask opening should be at least 0.0025" inwards from the edge of the PCB thermal pad. 5 XR16M780 D ESCRIPTION ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO Pin Description 32-QFN 48-TQFP 25-BGA N AME P # PIN 15 10, 12, 17, 20- 25, 29, 31, 34, 36, 37, 48 Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain. T YPE # Connects REV. 1.0.0 D ESCRIPTION ...
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... Flow Control, Automatic Xon/Xoff and Special Character Software Flow Control, infrared encoder and decoder (IrDA ver 1.0 and 1.1), programmable fractional baud rate generator with a prescaler of divide and data rate Mbps. The XR16M780 can operate from 1.62 to 3.63 volts. The M780 is fabricated with an advanced CMOS process. ...
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... The M780 data interface supports the Intel and Motorola compatible types of CPUs. No clock (oscillator nor external clock) is required for a data bus transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# or R/W# inputs. A typical data bus interconnection for Intel and Motorola mode is shown in Figure XR16M780 T I IGURE YPICAL NTEL D0 D1 ...
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... Serial Interface The M780 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422 transceivers www.exar.com or send an e-mail to uarttechsupport@exar.com XR16M780 T S IGURE YPICAL ERIAL ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO F 6. XR16M780 T S IGURE YPICAL ERIAL DTR# UART NTERFACE ONNECTIONS VCC VCC RTS# DE VCC RE# NC CTS# DSR# CD GND RS-485 Half-Duplex Serial Interface ...
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... PERATION FOR ECEIVER ) FCR B ISABLED LOW = FIFO below trigger level HIGH = FIFO above trigger level or RX Data Timeout HIGH = FIFO below trigger level LOW = FIFO above trigger level or RX Data Timeout 11 XR16M780 25. Table 1 and 2 Figure 22 through 25 (FIFO NABLED - (FIFO E ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.6 Crystal Oscillator or External Clock Input The M780 includes an on-chip oscillator to produce a clock for the baud rate generators in the device when a crystal is connected between XTAL1 and XTAL2 as show below. The CPU data bus does not require this clock for bus operation ...
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... Independent TX/RX BRG The XR16M780 has two independent sets of TX and RX baud rate generator. See work in different baud rate by setting DLD, DLL and DLM register. For example, TX can transmit data to the remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate setting, please See ” ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO IGURE AUD ATE ENERATOR Prescaler Divide by 1 Crystal XTAL1 Osc / XTAL2 Buffer Prescaler Divide ABLE YPICAL DATA RATES WITH A Required D 16x IVISOR FOR Output Data Clock O Rate (Decimal) ...
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... T O IGURE RANSMITTER PERATION IN NON Data Byte 16X Clock ( DLD[5:4] ) 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO -FIFO M ODE Transmit Holding Register THR Interrupt (ISR bit-1) (THR) Enabled by IER bit-1 M Transmit Shift Register (TSR XR16M780 TXNOFIFO1 ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.8.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the FIFO becomes empty ...
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... FIFO is Enabled bit-0=1 D ata fills to R TS# de-asserts w hen data fills above the flow 56 control trigger level to suspend rem ote transm itter. Enable by EFR bit-6= bit-1. R eceive D ata 17 XR16M780 Receive Data Characters RXFIFO1 M ODE R eceive D ata C haracters R X FIFO 1 ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.10 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features is enabled to fit specific application requirement (see • ...
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... RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend 9 RTS High RTS Low 5 RX FIFO Threshold Threshold 19 XR16M780 Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.13 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M780 will halt transmission (TX) as soon as the current character has completed transmission ...
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... Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin. Each time it senses a light pulse, it returns a logic 1 to the data bit stream. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO Figure 14 below. 21 XR16M780 Figure 14. ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO F 14 IGURE NFRARED RANSMIT ATA TX Data Transmit IR Pulse (TX Pin) Receive IR Pulse (RX pin) RX Data 2.17 Sleep Mode with Auto Wake-Up and Power-Save feature The M780 supports low voltage system designs, hence, a sleep mode with auto wake-up and power-save feature is included to reduce its power consumption when the chip is not actively used ...
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... The M780 has the wake up interrupt. By setting the FCR bit-3, wake up interrupt is enabled or disabled. The default status of wake up interrupt is disabled. Please Write-Only” on page 31. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO Figure 1 on page See ”Section 4.5, FIFO Control Register (FCR XR16M780 1) from other bus activities that ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 2.18 Internal Loopback The M780 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 15 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...
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... Read-only E R NHANCED EGISTERS Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 25 XR16M780 /W C RITE OMMENTS LCR[ LCR ≠ 0xBF, DLL = 0x00, DLM = 0x00 LCR[ LCR ≠ 0xBF See DLD[7:6] LCR[ LCR ≠ 0xBF, EFR[ LCR[ LCR[ EFR[ LCR ≠ 0xBF if EFR[ LCR ≠ ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO T 7: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/WR 0/ CTS# Int. Enable ISR RD FIFOs Enabled FCR WR RX FIFO Trigger ...
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... ISR [5:4], Flow FCR[5:3], Cntl MCR[7:5], Bit-3 DLD Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 Bit-6 Bit-5 Bit-4 Bit-3 27 XR16M780 EFR B -4 OMMENT Bit-2 Bit-1 Bit-0 LCR[ LCR≠0xBF DLL= 0x00 ...
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... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M780 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...
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... CTS# is when the remote transmitter toggles the input pin (from LOW to HIGH) during auto CTS flow control. • RTS# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS flow control. • Wakeup interrupt is generated when the M780 wakes up from the sleep mode. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 29 XR16M780 ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 4.4.2 Interrupt Clearing: • LSR interrupt is cleared by a read to the LSR register. • RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level. • RXRDY Time-out interrupt is cleared by reading RHR. • ...
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... Note that the receiver and the transmitter cannot use different trigger tables. Whichever selection is made last applies to both the RX and TX side. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 23. Table 9 below shows the selections. Note that the Table 9 31 XR16M780 shows the complete selections. ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table Table Table Table 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format ...
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... TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO S W TOP BIT LENGTH ORD ( LENGTH IT TIME S 5,6,7,8 1 (default) 5 1-1/2 6,7 10: P ABLE ARITY SELECTION -4 LCR ARITY SELECTION parity 0 1 Odd parity 1 1 Even parity 0 1 Force parity to mark, HIGH 1 1 Forced parity to space, LOW 33 XR16M780 ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO LCR[6]: Transmit Break Enable When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a “space’, logic 0, state). This condition remains, until disabled by setting LCR bit logic 0. ...
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... LSR[3]: Receive Data Framing Error Tag • Logic framing error (default). • Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with the character available for reading in RHR. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO Figure 35 XR16M780 15. ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO LSR[4]: Receive Break Tag • Logic break condition (default). • Logic 1 = The receiver received a break signal (RX was LOW for at least one character frame time). In the FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX input returns to the idle condition, “ ...
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... MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 4.10 Modem Status Register (MSR) - Write Only This register provides the advanced features of XR16M780. Lower four bits of this register are reserved. Writing to the higher four bits enables additional functions. MSR[3:0]: Reserved MSR[4]: Enable/Disable Transmitter (Requires EFR[ • ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 4.12 Enhanced Mode Select Register (EMSR) - Write-only This register replaces SPR (during a Write) and is accessible only when FCTR[ EMSR[1:0]: Receive/Transmit FIFO Level Count When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is operating in ...
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... IT (C HARACTERS ± ± ± ± ± ± ± ± ± ± ± ± ± ± ±36 Table 14 below and 39 XR16M780 ) 0 See ”Section 2.7, Programmable ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO DLD[5:4]: Sampling Rate Select These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will double if the 8X mode is selected and will quadruple if the 4X mode is selected. See ...
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... TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO Table ABLE RIGGER ABLE ELECT FCTR T ABLE Table-A (TX/RX) 1 Table-B (TX/RX) 0 Table-C (TX/RX) 1 Table-D (TX/RX) Table 17). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes 41 XR16M780 for more details. ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. T ABLE EFR -3 EFR -2 BIT BIT EFR ONT ...
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... These registers are used as the programmable software flow control characters xoff1, xoff2, xon1, and xon2. For more details, see Table 5. The xoff2 is also used as auto address detect register when the auto 9-bit mode enabled. See ”Section 2.15.1, Auto Address Detection” on page 21. 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 43 XR16M780 ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO REGISTERS DLM, DLL (Both TX and RX) DLD RHR THR IER FCR ISR LCR MCR LSR MSR SPR EMSR FC TRG FCTR EFR XON1 XON2 XOFF1 XOFF2 I/O SIGNALS TX RTS# DTR# INT (16 Mode) IRQ# (68 Mode) T 18: UART RESET CONDITIONS ...
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... IMITS IMITS 1.8V 2. -0.3 0.3 -0.3 0.4 1.4 VCC 2.0 VCC -0.3 0.2 -0.3 0.5 1.4 VCC 1.8 VCC 0.4 0.4 1.8 1.4 ±15 ±15 ±15 ± 1 XR16M780 3.6 Volts GND-0 3 - -65 to +150 C 500 C/W, theta- C C/W, theta- C C/W, theta-jc = 98.2 C/W L IMITS 3. NITS ONDITIONS -0.3 0.6 V 2.4 VCC V -0.3 0 ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO PAGE 23. To achieve minimum power drain, the voltage at any of the inputs of the M780 should NOT be lower than its VCC supply. AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER XTAL1 UART Crystal Frequency ...
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... LOAD WHERE APPLICABLE L IMITS 1.8V ± 10% 2.5V ± 10 16X data rate CLK OSC 47 XR16M780 L L IMITS IMITS 3.3V ± 10% U NIT Bclk ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO F 17 IGURE ODEM NPUT UTPUT 18 ...
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... RITE IMING Valid Data ATA US EAD IMING T T CSL ADH T CSD T RWH T RDH Valid Data 49 XR16M780 Valid Address Valid Data 16Write Valid Address Valid Data 68Read ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO F 21 IGURE ODE OTOROLA A0-A2 T ADS CS# T RWS R/W# D0- & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR ATA US RITE IMING Valid Address T T CSL ...
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... Stop D0:D7 Bit ISR is read T WRI T SRT [FIFO M ] IMING ODE D0:D7 D0:D7 D0: SSI RX FIFO fills Trigger Level or RX Data Timeout 51 XR16M780 D0:D7 ISR is read T WRI T SRT T WT TXNonFIFO D0:D7 D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXINTDMA# ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO F 25 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX S D0:D7 (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up to trigger level Data in TX FIFO TXRDY IOW# (Loading data into FIFO) *INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level ...
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... INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.193 0.201 4.90 0.138 0.150 3.50 0.007 0.012 0.18 0.0197 BSC 0.50 BSC 0.012 0.020 0.35 0.008 - 0.20 53 XR16M780 Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm MAX 1.00 0.05 0.25 5.10 3.80 0.30 0.45 - ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL INCHES MILLIMETERS ...
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... TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO ) (A1 corner feature is mfger option INCHES MILLIMETERS MIN MAX MIN 0.028 0.031 0.70 0.005 0.007 0.13 0.022 0.024 0.57 0.114 0.122 2.90 0.079 BSC 0.008 0.012 0.20 0.020 BSC 55 XR16M780 1 A1 corner MAX 0.80 0.19 0.61 3.10 2.00 BSC 0.30 0.50 BSC ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO REVISION HISTORY D R ATE EVISION September 2008 Rev 1.0.0 Final Datasheet. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement ...
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... PRODUCT DESCRIPTION ...................................................................................................................... 7 2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................. 8 2.1 CPU INTERFACE ................................................................................................................................................ XR16M780 IGURE YPICAL NTEL 2.2 SERIAL INTERFACE........................................................................................................................................... XR16M780 T S IGURE YPICAL ERIAL F 6. XR16M780 T S IGURE YPICAL ERIAL 2.3 DEVICE RESET ................................................................................................................................................. 11 2.4 INTERNAL REGISTERS.................................................................................................................................... 11 2.5 INT OUPUT ........................................................................................................................................................ INT ABLE IN PERATION FOR RANSMITTER T 2: INT P ...
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... XR16M780 1.62V TO 3.63V HIGH PERFORMANCE UART WITH 64-BYTE FIFO 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 28 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY .................................................................................. 29 4.4.1 INTERRUPT GENERATION: ........................................................................................................................................ 29 4.4.2 INTERRUPT CLEARING: ............................................................................................................................................. ABLE NTERRUPT OURCE AND RIORITY 4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY......................................................................................... FIFO T ...