xr16m890 Exar Corporation, xr16m890 Datasheet

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xr16m890

Manufacturer Part Number
xr16m890
Description
Uart With 128-byte Fifo And Integrated Level Shifters
Manufacturer
Exar Corporation
Datasheet

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NOVEMBER 2010
GENERAL DESCRIPTION
The
Universal Asynchronous Receiver and Transmitter
(UART) with integrated level shifters and 128 bytes of
transmit and receive FIFOs.
For flexibility in a mixed voltage environment, the
M890 has 4 VCC pins. There is a VCC pin for the
core, a VCC pin for the UART signals, a VCC pin for
the CPU interface signals and a VCC pin for the
GPIO signals. The VCC pins for the UART, GPIO
and CPU interface signals allow for the M890 to
interface with devices operating at different voltage
levels eliminating the need for external voltage level
shifters.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection and
Address
performance by simplifying the software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. In addition, the Fractional
Baud Rate Generator feature provides flexibility for
crystal/clock frequencies for generating standard and
non-standard baud rates.
The M890 has programmable transmit and receive
FIFO trigger levels, automatic hardware and software
flow control, and data rates of up to 24 Mbps. Power
consumption of the M890 can be minimized by
enabling the sleep mode.
The M890 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics.
Intel/Motorola/VLIO bus interface.
N
Exar
OTE
:
Corporation 48720 Kato Road, Fremont CA, 94538
XR16M890
1 Covered by U.S. Patent #5,649,122.
Byte
1
Control
(M890)
The M890 has a selectable
features
UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS
is
a
single-channel
increase
PRELIMINARY
the
(510) 668-7000
FEATURES
APPLICATIONS
Integrated Level Shifters on CPU interface, UART
and GPIO signals
Intel/Motorola/VLIO Bus Interface select
24 Mbps maximum UART data rate
Up to 16 GPIOs
128-Bytes TX and RX FIFOs
Programmable TX/RX trigger levels
TX/RX FIFO Level Counters
Independent TX/RX Baud Rate Generator
Fractional Baud Rate Generator
Auto RTS/CTS Hardware Flow Control
Auto XON/XOFF Software Flow Control
Auto RS-485 Half-Duplex Direction Control
Multidrop mode w/ Auto Address Detect (RX)
Multidrop mode w/ Address Byte Control (TX)
Sleep Mode with Automatic Wake-up
Infrared (IrDA 1.0 and 1.1) mode
1.62V to 3.63V supply operation
5V tolerant inputs
Crystal oscillator or external clock input
Personal Digital Assistants (PDA)
Cellular Phones/Data Devices
Battery-Operated Devices
Global Positioning System (GPS)
Bluetooth
’0’ ns address setup/hold times
’0’ ns data hold time
FAX (510) 668-7017
XR16M890
www.exar.com
REV. P1.1.1

Related parts for xr16m890

xr16m890 Summary of contents

Page 1

... Crystal oscillator or external clock input APPLICATIONS • Personal Digital Assistants (PDA) • Cellular Phones/Data Devices • Battery-Operated Devices • Global Positioning System (GPS) • Bluetooth • • (510) 668-7000 FAX (510) 668-7017 XR16M890 REV. P1.1.1 • www.exar.com ...

Page 2

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS F 1. XR16M890 B D IGURE LOCK IAGRAM VCC_BUS A2:A0 D7:D0 (AD7:AD0) CS# LLA# 1.62V- IOR# 3.63V IOW# (R/W#) I/O INT (IRQ#) Buffers RESET (RESET#) 16/68# VLIO_EN EN485# ENIR# XTAL1 XTAL2 SLEEP/PWRDN# ORDERING INFORMATION ART UMBER ACKAGE XR16M890IL32 QFN-32 ...

Page 3

... GPIO7 VCC_BUS 16/68 DSR#/GPIO1 AD0 2 35 CD#/GPIO2 AD1 3 34 RI#/GPIO3 AD2 4 33 GND AD3 5 XR16M890IM48 32 VCC_UART AD4 6 31 GPIO15 VLIO Mode AD5 7 30 GPIO14 AD6 8 29 GPIO13 AD7 9 28 GPIO4 IOR GPIO5 IOW GPIO6 CS GPIO7 3 XR16M890 ...

Page 4

... RI#/GPIO3 Intel (16) Mode 5 20 VCC_UART 6 19 RTS GND 1 24 DTR#/GPIO0 2 23 DSR#/GPIO1 3 22 CD#/GPIO2 XR16M890IL32 4 21 RI#/GPIO3 Motorola (68) Mode 5 20 VCC_UART 6 19 RTS VCC_BUS 1 24 DTR#/GPIO0 2 23 DSR#/GPIO1 3 22 CD#/GPIO2 ...

Page 5

... When 16/68# pin is at logic 0, the Motorola bus interface is selected and this input becomes read (logic 1) and write (logic 0) signal This input is chip select (active low) to enable the device. 5 XR16M890 D ESCRIPTION ...

Page 6

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS Pin Description QFN-32 QFN-40 TQFP-48 N AME P # PIN# PIN# IN INT 10 12 (IRQ#) RESET 9 10 (RESET#) DATA BUS INTERFACE - VLIO VLIO_EN 28 37 AD7 8 9 AD6 7 8 AD5 6 7 AD4 5 6 AD3 4 5 AD2 3 4 AD1 ...

Page 7

... These GPIOs are only available on the QFN-40 and TQFP-48 pack- 25 I/O ages. 19 I/O General purpose I/Os. 20 I/O 21 I/O These GPIOs are only available on the TQFP-48 package. 22 I/O 23 I/O 29 I/O 30 I Crystal or external clock input. Note: This input is not 5V tolerant Crystal or buffered clock output. 7 XR16M890 D ESCRIPTION ...

Page 8

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS Pin Description QFN-32 QFN-40 TQFP-48 N AME P # PIN# PIN# IN EN485 ENIR SLEEP PWRDN# (16/68#) VCC_CORE 25 34 VCC_BUS 12 15 VCC_UART 20 24 VCC_GPIO - 19 GND 11 14, 25 17, 33 GND Center Center Center Pad Pad Pad Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain ...

Page 9

... REV. P1.1.1 1.0 FUNCTIONAL DESCRIPTIONS 1.1 CPU Interface There are 3 CPU interfaces that can be selected on the XR16M890. They are the Intel, Motorola and VLIO bus interfaces. Note: no clock (crystal or external clock) is required for data bus transactions. Each bus cycle is asynchronous. 1.1.1 Intel bus interface (16 mode) The Intel bus interface consists of 8 data bits, 3 address lines and 3 control signals (CS#, IOR# and IOW#) for data bus read/write transactions ...

Page 10

... UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 1.1.3 VLIO bus interface The VLIO bus interface is similar to the Intel bus interface. The only difference is that the address and data lines are shared. A typical data bus interconnection is shown below XR16M890 T VLIO D IGURE YPICAL ...

Page 11

... Serial Interface The M890 is typically used with RS-232, RS-485 and IR transceivers. The following figure shows typical connections from the UART to the different transceivers. For more information on RS-232 and RS-485/422 transceivers www.exar.com or send an e-mail to uarttechsupport@exar.com XR16M890 T S IGURE YPICAL ERIAL ...

Page 12

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS F 8. XR16M890 T S IGURE YPICAL ERIAL VCC_UART UART PRELIMINARY I C NTERFACE ONNECTIONS VCC_UART RTS# DE VCC_UART RE# DTR# NC CTS# DSR# CD GND RS-485 Half-Duplex Serial Interface ...

Page 13

... ISABLED LOW = FIFO below trigger level HIGH = FIFO above trigger level or RX Data Timeout HIGH = FIFO above trigger level LOW = FIFO above trigger level or RX Data Timeout 13 XR16M890 may not be high enough OH “Section 2.0, UART INTERNAL Table 1 and 2 Figure 26 through 29 (FIFO E ...

Page 14

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 1.7 Crystal Oscillator or External Clock Input The M890 includes an on-chip oscillator to produce a clock for the baud rate generators in the device when a crystal is connected between XTAL1 and XTAL2 as show below. The CPU data bus does not require this clock for bus operation ...

Page 15

... Independent TX/RX BRG The XR16M890 has two independent sets of TX and RX baud rate generator. See use different baud rates by setting DLD, DLL and DLM register. For example, TX can transmit data to the remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate setting, See ” ...

Page 16

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS F 10 IGURE AUD ATE ENERATOR Prescaler Divide by 1 Crystal XTAL1 Osc / XTAL2 Buffer Prescaler Divide ABLE YPICAL DATA RATES WITH A Required Output D 16x IVISOR FOR Data Rate Clock (Decimal) ...

Page 17

... IGURE RANSMITTER PERATION IN NON Data Byte 16X Clock ( DLD[5:4] ) PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS -FIFO M ODE Transmit Holding Register THR Interrupt (ISR bit-1) (THR) Enabled by IER bit-1 M Transmit Shift Register (TSR XR16M890 TXNOFIFO1 ...

Page 18

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 1.9.3 Transmitter Operation in FIFO Mode The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the FIFO becomes empty ...

Page 19

... FIFO trigger level. FIFO is Enabled by FCR bit-0=1 Data fills to RTS# de-asserts when data fills above the flow 56 control trigger level to suspend remote transmitter. Enable by EFR bit-6=1, MCR bit-1. Receive Data 19 XR16M890 Receive Data Characters RXFIFO1 M ODE Receive Data Characters RXFIFO1 ...

Page 20

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 1.11 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control features is enabled to fit specific application requirement (see • ...

Page 21

... RTSA# CTSB# TXA RXB CTSA# RTSB# ON OFF 7 ON OFF 8 Restart 6 Suspend 9 RTS High RTS Low 5 RX FIFO Threshold Threshold 21 XR16M890 Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level FIFO 12 Trigger Level RTSCTS1 ...

Page 22

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 1.14 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the M890 will halt transmission (TX) as soon as the current character has completed transmission ...

Page 23

... Forced 1 parity, load the address byte in the THR, wait for the byte to be transmitted, change the parity back to Forced 0 parity, then load data into the TX FIFO. In the XR16M890, there’s no waiting required and no changing parity. The transmit routine can set SFR[7]=1, then write the address byte into the TX FIFO followed immediately by the data bytes ...

Page 24

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 1.19 Infrared Mode The M890 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0 and 1.1. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/ bit wide HIGH-pulse for each “ ...

Page 25

... Wake-up Interrupt The M890 has the wake up interrupt. By setting the FCR bit-3, wake up interrupt is enabled or disabled. The default status of wake up interrupt is disabled. Please Write-Only” on page 34. PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS See ”Section 3.5, FIFO Control Register (FCR XR16M890 ...

Page 26

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 1.21 Internal Loopback The M890 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally. Figure 17 shows how the modem port signals are re-configured. Transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to receive the same data that it was sending ...

Page 27

... EGISTERS Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 27 XR16M890 /W C RITE OMMENTS LCR[ LCR ≠ 0xBF, DLL = 0x00, DLM = 0x00 LCR[ LCR ≠ 0xBF See DLD[7:6] LCR[ LCR ≠ 0xBF, EFR[ LCR[ LCR[ EFR[ LCR ≠ ...

Page 28

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS T 7: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit THR WR Bit IER RD/WR 0/ CTS# Int. Enable ISR RD FIFOs Enabled FCR WR RX FIFO Trigger ...

Page 29

... Bit-13/ Bit-12/ Bit-11/ Bit-6 Bit-5 Bit-4 Bit-3 Bit-14/ Bit-13/ Bit-12/ Bit-11/ Bit-6 Bit-5 Bit-4 Bit-3 Bit-14/ Bit-13/ Bit-12/ Bit-11/ Bit-6 Bit-5 Bit-4 Bit-3 29 XR16M890 EFR B -4 OMMENT Send FIFO FIFO TX count count imme- control control LCR≠0xBF ...

Page 30

... IER versus Receive/Transmit FIFO Polled Mode Operation When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16M890 in the FIFO polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). ...

Page 31

... IER[7]: CTS# Input Interrupt Enable (requires EFR[4]=1) • Logic 0 = Disable the CTS# interrupt (default). • Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from LOW to HIGH (if enabled by EFR bit-7). PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 31 XR16M890 ...

Page 32

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 3.4 Interrupt Status Register (ISR) - Read-Only The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the ISR will give the user the current highest pending interrupt level to be serviced, others are queued serviced next ...

Page 33

... NABLE TATUS NTERRUPT E NTERRUPT NABLED GPIO I NTERRUPT ) EGISTER No No GPIO Interrupt Yes No GPIO Interrupt Yes GPIO Interrupt No No GPIO Interrupt Yes No GPIO Interrupt Yes GPIO Interrupt 33 XR16M890 L EVEL S OURCE OF INTERRUPT Table 8). S TATUS S ISR[7] ISR[6] TATUS ...

Page 34

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 3.5 FIFO Control Register (FCR) - Write-Only This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and enable the wake up interrupt. They are defined as follows: FCR[0]: TX and RX FIFO Enable • ...

Page 35

... Programmable via TRG register. FCTR[ BIT-0 W ORD LENGTH 0 5 (default XR16M890 L S EVEL ELECTION T RANSMIT T C RIGGER OMPATIBILITY L EVEL 1 (default) 16C550, 16x255x, 16x554, 16x57x, 16x58x 16 16C650A, 16L651, 16x265x, 16x564 16x654 16 32 ...

Page 36

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS LCR[2]: TX and RX Stop-bit Length Select The length of stop bit is specified by this bit in conjunction with the programmed word length. BIT LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check ...

Page 37

... Logic 0 = INT output disabled (three state). During internal loopback mode, OP2# is HIGH. • Logic 1 = INT output enabled (active). During internal loopback mode, OP2# is LOW. MCR B PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS T 12: INT O M ABLE UTPUT ODES INT O UTPUT - Three-State 1 Active 37 XR16M890 ...

Page 38

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS MCR[4]: Internal Loopback Enable • Logic 0 = Disable loopback mode (default). • Logic 1 = Enable local loopback mode, see loopback section and MCR[5]: Xon-Any Enable (requires EFR bit • Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default). ...

Page 39

... Logic global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the RX FIFO. PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 39 XR16M890 ...

Page 40

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 3.9 Setup/Hysteresis Register (SHR) - Write Only In the Auto RS-485 half-duplex mode, the RTS# control output can be asserted from bit times before data is transmitted to allow for the startup time of an RS-485 transceiver that may be in shutdown mode. The RTS# control output can also be delayed from bit times after the last byte has been transmitted to allow the data to propogate down long data cables ...

Page 41

... Logic change on CD# input (default). • Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem status interrupt will be generated if MSR interrupt is enabled (IER bit-3). PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 41 XR16M890 ...

Page 42

... MCR register. The CD# input may be used as a general purpose input when the modem interface is not used. 3.11 Special Function Register (SFR) - Write Only This register provides access to some of the advanced features of XR16M890. SFR[0]: Enable GPIO Registers • Logic 0 = GPIO control and status registers are not enabled. ...

Page 43

... A write will change the current value of the register. The current value of the register will also be the ■ current state of the output pin if three-state mode is not enabled (GPIO3T register). PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 43 XR16M890 See ...

Page 44

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 3.14 Enhanced Mode Select Register (EMSR) - Write-only This register replaces SPR (during a Write) and is accessible only when FCTR[ EMSR[1:0]: Receive/Transmit FIFO Level Count When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is operating in ...

Page 45

... TX and RX), this bit must be a logic 0 to properly write to the appropriate DLL, DLM and DLD[5:0]. PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS Table 15 below and T 15 ABLE AMPLING ATE ELECT DLD[ XR16M890 See ”Section 1.8, Programmable Table 15 below AMPLING ATE 16X 8X 4X ...

Page 46

... Feature Control Register (FCTR) - Read/Write FCTR[0]: SLEEP/PWRDN# Function Control • Logic 0 = SLEEP pin (input) is enabled. This pin can be used to force the XR16M890 to enter the sleep mode immediately after the next data byte that is being transmitted on the TX pin and being received on the RX pin has been completed. ...

Page 47

... flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS T 17 ABLE RIGGER ABLE ELECT FCTR T ABLE Table-A (TX/RX) 1 Table-B (TX/RX) 0 Table-C (TX/RX) 1 Table-D (TX/RX) Table 18). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes 47 XR16M890 ...

Page 48

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS EFR[3:0]: Software Flow Control Select Single character and dual sequential characters software flow control is supported. Combinations of software flow control can be selected by programming these bits. T ABLE EFR -3 EFR -2 EFR BIT BIT ONT ...

Page 49

... Logic 1 = GPIO interrupt is generated when this input pin is high. 3.24 GPIO Select Register (GPIOSEL) - Read/Write This register selects where a GPIO is an input or an output. • Logic 0 = GPIO is an output. • Logic 1 = GPIO is an input (default). PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS 49 XR16M890 ...

Page 50

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS REGISTERS DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power up. They do not reset when the Reset Pin is asserted. (Both TX and RX) DLD Bits 7-0 = 0x00 RHR Bits 7-0 = 0xXX THR Bits 7-0 = 0xXX ...

Page 51

... -0.3 0.3 -0.3 0.4 1.4 VCC_ 2.0 VCC_ CORE CORE -0.3 0.2 -0.3 0.5 1.4 5.5 1.8 5.5 0.4 0.4 1.8 1.4 ±15 ±15 ±15 ± 1 XR16M890 3.63 Volts GND-0 3. - -65 to +150 C 500 C/W, theta- C C/W, theta- C C/W, theta-jc = 10.5 C/W 3.63V L IMITS 3. NITS ONDITIONS -0.3 0.6 V (XTAL1 input) 2 ...

Page 52

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS AC ELECTRICAL CHARACTERISTICS - YMBOL ARAMETER XTAL1 UART Crystal Frequency ECLK External Clock Frequency T External Clock Time Period ECLK 16 Mode (Intel) Data Bus Read/Write Timing T Address Setup Time ...

Page 53

... Modem/Interrupt Timing 16X data rate 53 XR16M890 L L IMITS IMITS 3.3V ± 10% U NIT ...

Page 54

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS F 18 IGURE LOCK IMING CLK EXTERNAL CLOCK F 19 IGURE ODEM NPUT UTPUT ...

Page 55

... RDV Valid Data RITE IMING Valid Data 55 XR16M890 Valid Address Valid Data RDTm Valid Address Valid Data 16Write ...

Page 56

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS F 22 IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# T RWS R/W# T RDA D0- IGURE ODE OTOROLA A0-A2 T ADS CS# T RWS R/W# D0-D7 PRELIMINARY ATA US EAD IMING T T CSL ADH T CSD T RWH T RDH ...

Page 57

... IOW# PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS R T EAD IMING Lower Address LLA CSL T RDV T LLAR RITE IMING Lower Address Data LLA DS T CSL T LLAW XR16M890 Data ...

Page 58

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS F 26 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY NTERRUPT TX Start (Unloading) D0:D7 Bit IER[1] ISR is read enabled INT* T WRI ...

Page 59

... RX FIFO fills Trigger Level or RX Data Timeout T [FIFO M ] IMING ODE Stop Bit D0:D7 S D0:D7 T D0: trigger level T WRI 59 XR16M890 D0:D7 D0: FIFO drops below RX Trigger Level FIFO Empties T T RRI RR RXINTDMA# Last Data Byte Transmitted S D0:D7 D0: ISR is read ...

Page 60

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS PACKAGE DIMENSIONS (32 PIN QFN - 0.9 Note: The control dimension is in millimeter. SYMBOL PRELIMINARY ) mm INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.193 0.201 4.90 0.138 ...

Page 61

... INCHES MILLIMETERS MIN MAX MIN 0.031 0.039 0.80 0.000 0.002 0.00 0.006 0.010 0.15 0.232 0.240 5.90 0.189 0.197 4.80 0.007 0.012 0.18 0.0197 BSC 0.50 BSC 0.014 0.018 0.35 0.008 - 0.20 61 XR16M890 Note: the actual center pad is metallic and the size (D2) is device-dependent with a typical tolerance of 0.3mm MAX 1.00 0.05 0.25 6.10 5.00 0.30 0.45 - ...

Page 62

... XR16M890 UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL α PRELIMINARY ) INCHES ...

Page 63

... Copyright 2010 EXAR Corporation Datasheet November 2010. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. PRELIMINARY UART WITH 128-BYTE FIFO AND INTEGRATED LEVEL SHIFTERS D ESCRIPTION NOTICE 63 XR16M890 ...

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