xr16v2751im Exar Corporation, xr16v2751im Datasheet

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE SEPTEMBER 2007 GENERAL DESCRIPTION 1 The XR16V2751 (V2751 high performance dual universal asynchronous receiver and transmitter (UART) with 64 byte TX and RX FIFOs. The device operates from 2.25 to ...

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... RXB 4 RXA 5 XR16V2751 6 TXRDYB# 48-pin TQFP TXA (Intel) Mode TXB 8 OP2B# 9 CSA# 10 CSB# 11 PWRSAVE 12 ORDERING INFORMATION ART UMBER XR16V2751IM 48-Lead TQFP 36 RESET DTRB DTRA# RTSA OP2A# 31 RXRDYA# 30 INTA INTB CLKSEL VCC D6 2 ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 PIN DESCRIPTIONS Pin Description 48-TQFP N T AME YPE DATA BUS INTERFACE Address data lines [2:0]. These 3 address lines select one of ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE Pin Description 48-TQFP N T AME YPE INTB 29 O UART channel B Interrupt output. The output state is defined by the user through the software setting ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 Pin Description 48-TQFP N T AME YPE OP2A Output Port 2 Channel A - The output state is defined by the user and through ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE Pin Description 48-TQFP N T AME YPE 16/68 Intel or Motorola Bus Select. When 16/68# pin is HIGH Intel Mode, the device will ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 1.0 PRODUCT DESCRIPTION The XR16V2751 (V2751) integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and Transmitter (UART). Its features set is compatible to the XR16V2750 and XR16C2850 ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 2.3 Device Reset The RESET input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 17). An active high pulse ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE 2.7 DMA Mode The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t mean “direct memory access” but refers to data block ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 2.9 Crystal Oscillator or External Clock Input The V2751 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the device. The CPU ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number. When using a non- standard data rate crystal or external clock, the divisor ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0 ABLE YPICAL DATA RATES WITH A Required D 16x IVISOR FOR Output Data Clock O Rate (Decimal) 400 3750 2400 625 4800 312.5 9600 156.25 10000 ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE 2.11.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 2.12 Receiver The receiver section contains an 8-bit Receive Shift Register (RSR) and 64 bytes of FIFO which includes a byte-wide Receive Holding Register (RHR). The RSR uses the ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE IGURE ECEIVER PERATION IN 16X or 8X Clock (EMSR bit-7) Receive Data Shift Register (RSR) 64 bytes by 11-bit wide FIFO Data FIFO Receive Data Byte ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 2.15 Auto CTS Flow Control Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is monitored to suspend/restart the local ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE 2.16 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 2.19 Infrared Mode The V2751 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE 2.20 Sleep Mode with Wake-Up Indicator and PowerSave Feature The V2751 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave feature is included to reduce ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 2.21 Internal Loopback The V2751 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE 3.0 UART INTERNAL REGISTERS Each of the UART channel in the V2751 has its own set of configuration registers selected by address lines A0, A1 and A2 with CSA# or ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0 ABLE NTERNAL EGISTERS DDRESS EG EAD A2- AME RITE RHR RD Bit-7 ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE ABLE NTERNAL EGISTERS DDRESS EG EAD A2- AME RITE DLL RD/WR Bit ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the software flow control, receive Xoff interrupt (default). • Logic 1 = Enable the software flow control, receive ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0 ABLE P ISR R RIORITY EGISTER EVEL ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE FCR[2]: TX FIFO Reset This bit is only active when FCR bit ‘1’. • Logic transmit FIFO reset (default). • Logic 1 = Reset the ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 T 11: T ABLE RANSMIT AND T FCTR FCTR FCR RIGGER ABLE Table ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE LCR[3]: TX and RX Parity Select Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data integrity check. ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 MCR[0]: DTR# Output The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a general purpose output. • ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE 4.8 Line Status Register (LSR) - Read Only This register provides the status of data transfers between the UART and the host. LSR[0]: Receive Data Ready Indicator • Logic 0 ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 MSR[0]: Delta CTS# Input Flag • Logic change on CTS# input (default). • Logic 1 = The CTS# input has changed state since the last time ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE EMSR[1:0]: Receive/Transmit FIFO Level Count (Write-Only) When Scratchpad Swap (FCTR[6]) is asserted, EMSR bits 1-0 controls what mode the FIFO Level Counter is operating in. T FCTR[6] EMSR[1] EMSR[0] Scratchpad ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 EMSR[6]: LSR Interrupt Mode • Logic 0 = LSR Interrupt Delayed (for 16C2550 compatibility, default). LSR bits 2, 3, and 4 will generate an interrupt when the character with ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE FCTR[2]: IrDa RX Inversion • Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW). • Logic 1 = Select RX input as inverted encoded ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 T ABLE EFR -3 EFR -2 EFR BIT BIT ONT ONT ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE EFR[6]: Auto RTS Flow Control Enable RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is selected, an interrupt will ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 T 17: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLM, DLL DLM = 0x00 and DLL = 0x01. Only resets to these values during a power ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (48-TQFP) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS O ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED 3.63V LOAD WHERE APPLICABLE S P YMBOL ARAMETER XTAL1 UART Crystal Oscillator ECLK External Clock T ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE AC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED 3.63V LOAD WHERE APPLICABLE S P YMBOL ARAMETER T Delay From IOR# To Reset Interrupt RRI T ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0 IGURE ODEM NPUT UTPUT IOW # Active RTS# Change of state DTR# CD# CTS# DSR# INT IOR# RI ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE F 16 IGURE ODE NTEL ATA A0-A2 Valid Address T AS CSA#/ CSB# IOW# D0- IGURE ODE OTOROLA ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0 IGURE ODE OTOROLA A0-A2 Valid Address T ADS CS# T RWS R/W# D0- & I IGURE ECEIVE EADY ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE F 20 & I IGURE RANSMIT EADY NTERRUPT TX Start D0:D7 Bit IER[1] ISR is read enabled INT* T WRI T SRT TXRDY IOW# (Loading data ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0 & I IGURE ECEIVE EADY NTERRUPT Start Stop Bit Bit RX D0:D7 D0: INT RX FIFO fills Trigger Level or ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE F 24 & I IGURE RANSMIT EADY NTERRUPT Stop Start Bit Bit TX S D0: D0:D7 (Unloading) IER[1] ISR Read enabled INT* TXRDY# IOW# (Loading data ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 PACKAGE DIMENSIONS (48 PIN TQFP - Seating Plane Note: The control dimension is the millimeter column SYMBOL ...

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... Corrected the maximum crystal frequency. EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...

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HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE REV. 1.0.1 GENERAL DESCRIPTION................................................................................................ 1 A .............................................................................................................................................. 1 PPLICATIONS F .................................................................................................................................................... 1 EATURES F 1. XR16V2751 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT ...

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XR16V2751 HIGH PERFORMANCE DUART WITH 64-BYTE FIFO AND POWERSAVE FEATURE 4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE................................................................................. 24 4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................... 25 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION .................................................................. 25 4.4 INTERRUPT ...